About the role

Emulation Engineer – Cadence Palladium Platform

Location: Remote

Experience: 5–7+ Years (4+ Years on Palladium preferred)

Employment Type: Contract

Role Overview

We are seeking an experienced Emulation Engineer with strong hands-on expertise in the Cadence Palladium emulation platform, particularly in system build-up, compilation, partitioning, and bring-up processes. The ideal candidate will have deep understanding of hardware verification, SoC-level validation, and emulation performance optimization.

Key Responsibilities

Lead and manage Palladium build-up and bring-up activities for complex SoC/ASIC designs
Perform design compilation, partitioning, and mapping onto the Palladium platform
Optimize emulation performance, debug compile/runtime issues
Support RTL integration, testbench adaptation, and synthesis readiness
Work closely with RTL, DV, and firmware teams for smooth emulation deployment
Configure and maintain emulation environment, including host interfaces and transactors
Troubleshoot capacity, timing, and memory-related build failures
Enable HW/SW co-verification and early firmware validation
Automate build and regression flows using scripting (Python/Shell/TCL)

Required Technical Expertise

Core Skills

Strong hands-on experience with Cadence Palladium (Z1/Z2/XP or latest variants)
Deep understanding of emulation build flow, partitioning strategies, and design bring-up
Experience with RTL (Verilog/SystemVerilog/VHDL)
Knowledge of Synthesis concepts and gate-level design constraints
Debugging experience in emulation environment

Verification & System Knowledge

Experience in SoC-level verification
Familiarity with UVM-based environments
Understanding of HW/SW co-verification flows
Exposure to PCIe, DDR, Ethernet, or other high-speed interfaces (preferred)

Tools & Scripting

Strong scripting skills in Python / TCL / Shell
Experience with version control systems (Git, Perforce)
Familiarity with job schedulers and regression frameworks

Preferred Qualifications

Experience in large SoC (>10M gates) emulation environments
Knowledge of performance tuning and capacity management
Exposure to FPGA prototyping is a plus
Good understanding of Linux-based development environments

Soft Skills

Strong debugging and problem-solving skills
Ability to work cross-functionally with global teams
Clear communication and documentation abilities

Nice to Have

Experience in AI/ML accelerator or networking SoC projects
Experience in silicon bring-up support

Detailed Candidate Qualifications

In more detail, the candidate should have the qualifications as listed below:

SystemVerilog
UVM based VIP integration
C/C++
MIPI CSI-2, HDMI 2.0, LPDDR4, eMMC 5.1, QSPI, UART interface protocols
Emulation with Palladium including:
- Compilation
- Debug
- Performance tuning
- Integration with memory models
- Integration with SpeedBridge Adapters
- Integration with AVIPs
Tcl
Python
Git