Microchip-Bangalore_RTL Design_7 to 15+years

Microchip- Bangalore

Senior Engineer I - Design

Job Description:

The Wireless Solutions Group is seeking an experienced Senior Engineer I - Design for our next generation high-performance, low-power wireless SoC and attach solutions. In this role, you will be responsible for the design of System-on-Chip (SOC) solutions for wireless applications. You will collaborate closely with cross-functional teams, including verification, analog, validation, and software engineers, to deliver high-quality products. Successful candidate requires strong collaboration across sites and functions, excellent communication, and the ability to thrive in a fast-paced, dynamic environment.

Key Responsibilities:

·         Contribute to SOC design from concept to tape-out.

·         Implement SOC designs according to micro-architecture specifications and design documentation, performing RTL coding, synthesis, timing analysis, and executing the SOC design flow to ensure IC qualification meets required standards.

·         Collaborate with verification teams to ensure thorough design verification according to test plans.

·         Work with physical design teams to ensure successful integration and implementation.

·         Participate in design reviews to ensure compliance with design standards and project requirements.

·         Support the validation team in qualifying silicon ICs and debugging potential issues.

·         Contribute to the development and optimization of low-power design techniques and power estimation methodologies.

·         Interfacing with external vendors and IP sources to resolve problems.

·         Ability to work well in a team and excellent problem solving, verbal and written communication skills.

·         Working with members from international design and implementation teams

Requirements/Qualifications:

·         Bachelor's or master’s degree in computer engineering, electrical engineering, or related field.

·         Minimum 7+ years of experience in digital SOC design, with a focus on low-power design.

·         Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint (SDC) and timing analysis.

·         Experience with ASIC design flow including LINT, Formal, CDC/RDC, power estimations, MBIST/DFT concepts, and low-power design techniques.

·         Strong understanding of SOC architecture (ARM/MIPS), bus protocols (AMBA, AXI, etc.), and peripheral IPs (USB, Ethernet, I2C, SPI, etc).

·         Experience with Bus Matrix design.

·         Experience with script Language such as TCL, Perl, and Python.

·         Excellent English reading, writing and verbal communication skills.

·         Strong analytical and problem-solving skills.

·         We are looking for candidates who are self-motivators, energetic, and team players.

Preferred Skills and Experience:

·         Knowledge of Bluetooth/BLE/Wi-Fi communication theory and standard specifications.

·         Knowledge of security features and principles of functional safety–compliant design.

·         Experience with verification methodologies (UVM/OVM).

·         Experience with validation methodologies, including debugging on FPGA and silicon IC boards.

Travel Time: 0% - 25%

 

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