RTL Design

Experience – 7 to 16+Years

Job Location- Bangalore

Job Role:  ASIC Design / Digital Desing

Req Title :  Principal / Senior Principal Engineer

Experience :  10-15 Years

Responsibilities

We are looking for engineers to join our team working on some of our most innovative and successful products.

What you would work on

Micro architect, implement and verify the digital processing blocks which are part of a CMOS Image Sensor.

Interact with multiple cross functional teams on requirements and deliverables.

Fault injection simulations and analysis to improve the coverage and help meet the ASIL requirements.

Contribute to design methodology improvement.

 

Qualifications

 

BE/ME in electronics or related technical field.

At least 10 years of relevant experience in semiconductor product development.

Experience going through full ASIC development cycle including concept, specification, design, verification and documentation.

Experience in working on data path elements, control logic, design for synthesis, multi clock domain designs, low power design techniques and behavioural modelling.

Knowledge of System Verilog and scripting and familiarity with C modelling.

Should have good analytical skills for debug work needed during verification.

Good written and verbal communication skills.

Experience with the following is an advantage but not a requirement:

Knowledge of image sensor design.

Understanding of a typical mixed signal system requirement.

 

Job Role:  ASIC Design / Digital Desing

Req Title :  Principal / Senior Principal Engineer

Experience :  10-15 Years

Key Responsibilities

Lead architecture definition and circuit design of OTP and EEPROM memory IPs, including bit-cell, periphery, high-voltage devices, charge pumps, sense amplifiers, and write/erase control.

Define programming algorithms, redundancy schemes, reliability mechanisms, and safety features.

Drive PPA (Power, Performance, Area) optimization across multiple technology nodes.

Own top-level NVM IP micro-architecture, including interfaces to digital controllers and test logic.

Responsibilities for Internal Candidates  

Implementation & Silicon Execution

 

Oversee schematic design, simulation, and verification (functional, corner, Monte-Carlo, aging).

Partner closely with layout teams to ensure DRC/LVS clean, robust HV-aware layouts with strong EM/IR and reliability margins.

Support DFT, BIST, IJTAG, and test-mode implementation, including fuse evaluation and trimming flows.

Drive silicon bring-up, debug, and characterization, including programming window optimization and yield learning.

Define and support qualification strategies (HTOL, bake, cycling, retention, endurance).

Work with Quality & Reliability teams to ensure product readiness and cost-effective qualification.

Own failure analysis and root-cause resolution for NVM-related issues.

Cross-Functional Leadership

 

Act as technical lead interfacing with Technology Development, Digital Design, Validation, Product, and Foundry partners.

Mentor junior and mid-level designers; establish best practices and design methodology for NVM IP.

Contribute to multi-generation NVM roadmaps and technology scaling strategies.

Qualifications for Internal Candidates     

Required Qualifications

 

Bachelor’s or Master’s degree in Electrical Engineering or related field.

10+ years of hands-on experience in OTP and/or EEPROM memory design.

Strong expertise in:

NVM bit-cell and peripheral circuit design

High-voltage devices and reliability-aware design

Programming/erase algorithms and margin analysis

Silicon debug and characterization

Proficiency with SPICE simulation, corner analysis, and statistical modeling.

Experience working across multiple process nodes and foundry technologies.

Preferred Qualifications

 

Experience with both OTP and EEPROM (cell-based or fuse-based implementations).

Familiarity with automotive or safety-critical requirements (AEC-Q100, ISO-26262).

Exposure to NVM controllers, digital interfaces, and test vehicles.

Prior experience leading IP tape-outs and production releases.

Strong documentation and technical review skills.

Job Role -Digital Design

Req Title-   Snr Principal Digital Design Engineer

Experience -12+Years

 

· Work with different product lines for SoC RTL implementation of power driver digital controls for LED/SiC/smartFET/Efuse application, peripherals like I2C, SPI, LIN, CAN protocols 

· The candidate will work on digital design architecture, digital RTL, low power design, synthesis and timing analysis with PD engg, Physical Design (PD) interface for the power management chips 

· The candidate will be able to work as part of a large and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies

· Define and implement micro-architecture to RTL implementation with the refining of features requirements throughout the design process

· Support the bring-up of various features at a system level in various pre-silicon platforms like SOCV, Emulation, FPGA.

· Own technical outcome of design, verification, implementation, and execution of Power Management ICs with complexities that can span from simple regulators to complex designs, control loops, and digital interfaces  

· Understand project goals, execute with realistic schedule, report status of progress  and understand clarity of project details and milestones 

· Lead and support Customer issues, Production issues, FW and System development, Failure Analysis

· Support post-silicon validation activities for your designs.