Physical design

LOCATION - BANGALORE

EXPERIENCE - 5+ yrs

Job Description:

Microchip’s DSPIC Business Unit is seeking a skilled and experienced Physical Design Engineer to join our global DSPIC Physical Design team. In this role, you will be instrumental in driving the successful execution of microcontrollers and microcontroller-based SOC designs, delivering the next generation of hierarchical, low power, mixed signal microcontroller solutions.

Key Responsibilities:

• Implement complex mixed signal, low power designs using state-of-the-art FLASH process technologies.
• Work independently and efficiently on assigned project responsibilities, from new design exploration through delivery of GDS (netlist to GDSII flow) and Metal-only ECO implementation.
• Provide Physical Design support for test chip shuttles, including development work associated with new concepts and flow.
• Develop and enhance Physical Design flow and methodology, including comprehensive documentation.
• Conduct power integrity and reliability analysis, ensuring robust sign-off for all designs.
• Mentor and provide guidance to junior team members, fostering a collaborative and growth-oriented environment.

Detailed Job function:

• Conduct floorplan exploration and optimization for accurate die size estimation.
• Perform power domain and voltage area-based floor planning, including power grid planning and implementation.
• Execute placement and optimization with a focus on timing, area, and power efficiency.
• Manage clock tree synthesis, balancing, and debugging to ensure robust clock distribution.
• Drive post-route timing optimization and timing closure to meet design specifications.
• Perform timing and signal integrity analysis at both chip and block levels.
• Ability to lead chip and block level physical implementation activities.
• Develop and refine physical design flow and methodology for improved efficiency and quality.
• Conduct physical verification, including DRC (Design Rule Check) and LVS (Layout Versus Schematic).
• Ensure IR drop and electromigration (EM) signoff for reliable power delivery.
• Implement timing and metal-only ECOs (Engineering Change Orders) as needed.
• Interface with internal and external IP teams, as well as CAD vendors, to resolve technical issues.
• Collaborate closely with synthesis, DFT, and other cross-functional global teams to achieve timely tapeout and ensure first-pass working silicon.

Requirements/Qualifications:

• Minimum of 5 years of hands-on experience in Physical Design and related technical areas, demonstrating a strong track record of successful project execution.
• Advanced knowledge of place and route methodologies, as well as low power physical design flows and methodologies.
• Proficiency with industry-standard physical implementation and analysis tools such as Innovus or Fusion Compiler, Calibre, Redhawk, Starrcxt, QRC, or equivalent EDA tools.
• Strong scripting skills in TCL, PERL, and Shell, along with working knowledge of hardware description languages such as Verilog and VHDL.
• Excellent analytical and debugging abilities, with a proactive approach to identifying and resolving technical challenges.
• Independent, self-motivated, and capable of managing responsibilities.
• Outstanding oral and written communication skills, with the ability to clearly convey technical concepts and collaborate effectively within a team.
• Familiarity with advanced nodes is desirable.