RTL Design Engineer

Job Description
Job Title: ASIC Design Engineer (5+ years experience)
Primary Location: Hyderabad
Role Summary:
Kinara focuses on edge AI technology, committed to pushing the boundaries
of what’s possible in machine learning and artificial intelligence. We develop state-of-the-
art AI processors, on-chip high speed interconnects that deliver unmatched performance,
power efficiency, and scalability to meet the demands of modern AI applications. We also
work on high speed interfaces like DDR, PCIE, USB etc. We are seeking a highly skilled and
motivated VLSI Design Engineer to join our dynamic team. The ideal candidate will have a
strong background in VLSI design, IP design, IP integration into SOC, Design Debug skills,
synthesis, LEC, timing clean up, lint/CDC/CLP/UPF .This role involves working on cutting-
edge semiconductor projects and requires a combination of technical expertise, problem-
solving skills, and the ability to work collaboratively within a team environment. 

Job Responsibility:
Add a maximum of 10 bullets of key tasks in this role
Tip: use keywords that are most likely to be searched on by your candidates

 Define micro-architecture and write detailed design specifications. 
 Develop RTL code based on system-level specifications using Verilog, VHDL,
or SystemVerilog. 
 Implement complex digital functions and algorithms in RTL. 
 Create and execute detailed test plans to verify RTL designs. 
 Optimize designs for power, performance, and area (PPA) constraints. 
 Perform simulation and debugging to ensure design correctness. 
 Work with verification engineers to develop test benches and validate RTL against
specifications. 
 Strong understanding of digital design principles and concepts. 
 Proficiency in writing and debugging RTL code. 
 Experience with synthesis, static timing analysis, and linting tools. 
 Familiarity with scripting languages such as Python, Perl, or TCL for automation. 
 Experience in any of processor subsystem design, interconnect design, high speed IO
interface design. 

NXP Semiconductors, High Tech Campus 60, 5656 AG Eindhoven, The Netherlands INTERNAL
www.nxp.com
Job Qualification:
Add a maximum of 15 bullets to indicate to what person this job makes sense for
(education/major) bachelor's degree or above in XX or equivalent
experience
 Bachelor’s or Master’s degree in Electrical Engineering, Computer
Engineering, or related field. 
 5+ years of experience in RTL design and verification. 
 Proven experience with digital logic design using Verilog, VHDL,
or SystemVerilog. 
 Experience with simulation tools such as VCS, QuestaSim, or similar. 
 Hands-on experience with RTL design tools (e.g., Synopsys Design Compiler,
Cadence Genus).