IBM-Bangalore_ DFT Lead_10 to 20+years

IBM Labs-Bangalore 

DFT Lead 

Experience: 10 to 20+years 

Your role and responsibilities 

We are seeking an experienced Design For Test (DFT) Technical Lead to own and drive the DFT architecture, methodology, and quality for complex ASIC / SoC designs. 

This role is a senior technical leadership position responsible for defining DFT solutions, ensuring coverage and test quality, and enabling predictable execution through close collaboration with design, physical design, validation, test, and program management teams. 

The candidate must have deep hands-on DFT expertise, strong architectural judgment, and the ability to mentor teams while guiding programs through tape-in, tape-out, and post-silicon execution. 

Required education: Bachelor's Degree 

Preferred education: Master's Degree 

Required technical and professional expertise 

12+ years of experience in DFT for ASIC / SoC designs 

Proven hands-on expertise in: 

Scan, compression, ATPG, and coverage analysis 

MBIST, LBIST and test methodologies 

JTAG /IJTAG and test access mechanisms 

Strong understanding of: 

RTL-to-GDSII flows 

Physical design impacts on DFT 

Silicon debug and production test requirements 

Experience driving DFT quality through multiple successful tape-outs 

Good understanding of fault models and coverage improvement techniques 

Ability to make sound technical decisions under schedule and complexity constraints 

Experience in leading DFT teams and driving team to meet test quality targets and schedule 

Strong communication, problem solving , collaboration and leadership skills 

Preferred technical and professional experience 

Experience with large, multi-chip programs or complex SoCs 

Familiarity with low-power DFT, hierarchical DFT, or test reuse strategies 

Exposure to advanced technology nodes and high-performance designs 

Prior experience influencing or defining DFT methodology at an organizational level