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Connect Pro Management Consultants
MosChip_Physical Design_Hyderabad
Connect Pro Management Consultants · posted 6 months ago
Andhra Pradesh, Hyderabaddesign and development
About the role
PD Lead:
- He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
- Minimum of 7-15 years of experience in physical design.
- He/She should have worked on 7nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.
- Provide technical guidance, mentoring to physical design engineers.
- Lead a team of Physical design engineers and be responsible for their blocks’ closure
- Interface with front-end ASIC teams to resolve issues.
- Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.
- Expertise in Timing closure on high speed interfaces is a plus
- Excellent communication skills.
- Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
- Extensive experience and detailed knowledge in Cadence or Synopsys.
- Expertise in scripting languages such as PERL, TCL.
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Strong Physical Verification skill set.