Principal Engineer - Implementation

Job Responsibilities:

 

The employee is responsible for implementation activities of multiple large & complex blocks & sub-system implementation from 16nm to 3nm and below technology nodes. The employee is expected to take ownership of Full Chip/Subsystem complex design & flow challenges, which would include:

• Perform Synthesis and STA timing closure for multi-million hierarchical complex designs.
• Lead and drive team members to complete Implementation activities.
• Complete timing closure for blocks & top level in advanced nodes.
• Develop constraints/SDC and perform pre & post-layout timing closure.
• Perform CLP and LEC for both full chip and block level.
• Experience on UPF/CPF would be an added advantage.
• Optimize design performance through timing closure and power optimization.
• Develop and maintain design constraints and timing models.
• Analyze and debug timing issues.
• Inserting DFT logic for both block and top level.
• Analyze Physical timing challenges and provide guidance for placement & CTS.
• Occasional travel needed.
• Use metric-driven techniques to help ensure first-pass working silicon.
• Communicate regularly with the implementation and project team to resolve issues, and communicate status to Project Management.

 

Job Qualifications:

This position requires at least B.E/B.Tech/M.Tech in Electronics with 9+ years to 12Yrs of Synthesis & STA experience in a fast-paced environment with following experience.

• Expertise in Implementation activities: Synthesis, STA, LEC, Low Power Checks.
• Static Timing/Crosstalk Analysis and timing closure
• Must have understanding of DFT insertion.
• Expertise with Synthesis & STA Tools (Genus, Fusion Compiler, Primetime or Tempus).
• Experience on Conformal LEC and CLP will be added advantage.
• Strong programming knowledge in Perl, TCL, and/or Shell and Python Scripting
• Excellent oral and written communications skills to work with teams across the globe
• Strong understanding of timing closure and power optimization techniques
• Must have good understanding of Verilog