IP Design Verification Lead Engineer

Position Overview

NovaRays Semi is seeking a highly motivated Design verification lead to contribute to the development and delivery of world-class Analog  IPs for leading semiconductor customers.

Key Responsibilities

·         Define a analog IP verification strategy and   test plan   through specification (A-Spec) document

·         Development of   testbench, test-bench components for   Analog IP Data, Clock and Control Paths.

·         Leading the 4-5 member verification team and verification execution

·         Defining and meeting   a coverage goals (functional, code coverage, and feature coverage)

·         Adhering to coding guideline practices, develop and implement code review process.

·         Collaborate with global design verification teams and other stakeholders

·         Working with SOC team on

Minimum Qualifications

·         Bachelor’s degree in electrical engineering with 8-10 years   experience of Design Verification.

·         Experience in Analog IP along with knowledge of industry standard analog IP architecture, and protocols such as PCIE, DDR, and UCIE

·         Strong understanding of the design and verification life cycle, QOV, and coverage goals

·         Hands on verification experience with C/C++/SystemVerilog testbench development.

·         Hands on experience with coverage planning, coding and coverage closure.

·         Experience in clocking, reset, power-up sequences and power management verification.

·         Understanding of low power design verification techniques is a plus.

·         Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion.

Desired Qualifications

·         Experience of verification of  complex analog/Digital boundary interface.

·         Validation Coverage through AMS, DV and formal verification

·         Post-Silicon debug experience