DFT

 

Experience - 7+ yrs

LOCATION - BANGALORE

ASIC Design DFT engineer with  10+ years  of related work experience with a broad mix of technologies including:

Knowledge of the latest state of the art trends in Memory testing and silicon engineering

Hands on experience in JTAG & IJTAG protocols, MBIST and scan architectures.

Verification skills including System Verilog, LEC and validating test timing of the design

Experience working with gate-level simulations, and debug with VCS and other simulators

Understanding the testbench in System Verilog, UVM/VMM is addon

Post-silicon validation and debug experience, ability to work with ATE patterns

Strong verbal communication skills and ability to thrive in a dynamic environment

Scripting skills: Python/Perl