Physical Design- Sr Staff- 5+yrs

Your Role

Key responsibilities in your new role:
 

• This position is for Physical Design and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets.

• Candidate will be responsible to drive die area, performance, power goals for hierarchical blocks/Top.

• Candidate will work on various stages of physical design implementation which includes floor planning, IO planning, packager co-design, power grid design, place and route, clock tree synthesis, timing closure, Static/Dynamic IR drop, physical verification checks.

• Candidate is expected to have deep understanding and hands-on experience in implementing SOCs with multiple voltage islands, power islands and other power reduction techniques.

• Candidate should have good understanding of IO planning, package co-design aspects.

• Candidate is expected to drive flow/methodology activities to improve upon QoR.

Your Profile

Qualifications and skills to help you succeed
 

• Bachelor's or Master's degree with specialization in VLSI design

• Must have 8+ years of hands-on experience in physical design and timing closure of SoCs

• Experience of industry standard tools for physical design and signoff

• Experience in scripting languages (shell, perl, tcl) and Make flow

• Understanding of 40nm/28nm/22nm technologies and associated physical design challenges

• Must be a good team player and should have desire to learn and explore

• Strong commitment and determination in area of expertise

• Must be well organized, methodical and detail oriented

• Takes initiatives and overcomes challenges through creativity and innovation

• Coordinates with colleagues and actively shares expertise with others

• Shares information comprehensively and effectively