Verification Engineer

Company - Microchip

Job location- Hyderabad

Experience - 14 to 20+Years

 

Key Responsibilities

· Lead full-chip verification methodology planning, setup and execution for first-silicon success.

· Architect and implement SystemVerilog-based UVM/OVM testbenches, assertions, formal checks, gate-level simulations (GLS) and related functions.

· Collaborate across architecture, design, and post-silicon teams to ensure robust verification coverage for first-silicon success.

· Drive emulation and hardware prototyping strategies for complex digital and mixed-signal subsystems.

· Build and mentor a high-performing verification team, including performance management and career development.

· Foster a collaborative, teamwork-oriented culture across global teams.

· Continuously evaluate and adopt industry-leading verification methodologies and tools.

Requirements/Qualifications:

Required Qualifications

· Minimum 15+ years of relevant experience in digital and mixed-signal verification; 20+ years preferred.

· Experience with FPGA or ASIC SoC development is highly desirable.

· Proven expertise in presilicon verification, including UVM/OVM, formal verification, and GLS.

· Strong understanding of adjacent domains such as design, architecture, emulation, and post-silicon validation.

· Demonstrated success in leading verification teams and delivering first-silicon success.

Preferred Attributes

· Strategic mindset with a passion for methodology innovation and continuous improvement.

· Excellent communication and cross-functional collaboration skills.

· Experience in succession planning, team building, and technical staff development.