Digital Design Engineer

Key Responsibilities

·                 Micro‑architect and implement deeply pipelined digital filters and signal‑conditioning blocks (FIR/IIR, decimators/interpolators, half‑band, CIC where appropriate).

·                 Define and manage fixed‑point Q‑formats (e.g., U14.4, S16.8): scaling, coefficient quantization, rounding , saturation/overflow policy, and guard‑bit planning.

·                 Build high‑frequency datapaths using pipelining/retiming, carry‑save MAC trees, and efficient use of multiplier/DSP resources to meet aggressive Fmax/throughput targets.

·                 Design control/status/register maps and integrate with SoC bus interfaces (e.g., AHB/AXI).

·                 Collaborate with control‑systems engineers to implement digital compensator infrastructure (e.g., PID/biquads, anti‑windup, rate limiting

·                 Coordinate with mixed‑signal and system teams on sampling boundaries, data alignment, and latency budgets across ADC/DAC and actuation interfaces.

·                 Ensure robust sign‑off: lint/CDC/RDC, reset/clocking strategies, power intent (UPF/power gating), and clean synthesis handoff.

·                 Support verification and bring‑up from block level to system integration.

Modeling, Verification, and Tooling

·                 Develop and maintain MATLAB/Simulink fixed‑point golden models; generate stimuli/expected results and acceptance criteria from these models.

·                 Establish a bit‑true correlation flow between models and RTL, including rounding/saturation policies and latency alignment; automate regressions (e.g., Python/C++).

·                 Define test plans covering min/max/near‑saturation cases, coefficient extremes, multirate edges, and performance/SNR checks.

Mandatory

·                 Proven experience micro‑architecting and delivering RTL IP from scratch; strong Verilog/SystemVerilog and ASIC development flow expertise.

·                 Demonstrated success with high‑speed algorithmic datapaths and aggressive timing closure (pipelining, retiming, logic optimization).

·                 Solid command of fixed‑point arithmetic (adds/mults/MACs, scaling, rounding, saturation) and Q‑format design.

·                 Experience with lint/CDC/RDC, synthesis/PD collaboration, and SoC bus/register integration.

Preferred

·                 Hands‑on design of FIR/IIR filters (including polyphase/half‑band, CIC) and fixed‑point coefficient quantization.

·                 MATLAB/Simulink proficiency for fixed‑point modeling and bit‑true verification; experience building automated correlation flows.

·                 Exposure to digital control‑loop implementations (PID/biquads) and guardrail logic, with willingness to ramp on control theory.

·                 Experience interfacing with mixed‑signal blocks (ADC/DAC), calibration, and latency/throughput co‑design