About the role

Core Logic Design Lead

Bangalore, Karnataka, India

Introduction

At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You’ll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.

Your role and responsibilities

Collaborate with micro architect, designers to propose and demonstrate the core CPU and Fabric micro architectural features to drive performance per area/power on targeted workloads.
Collaborate with Silicon Bringup team and Software team to verify and debug microarchitecture and its performance.
Strong ability to communicate and drive to closure micro architectural proposals within Cache and coherent Fabric with technical stakeholders across Chip/System with presentation and documents.
Strong collaborative and interpersonal skills and a proven ability to guide new design team members

Required education

Bachelor's Degree

Required technical and professional expertise

10 – 15 years experience in high performance microprocessor architecture, micro architecture, computer architecture.
Deep knowledge of Processor Instruction set architecture (e.g ARM, X86, Power).
Deep understanding/experience of CPU microarchitecture and architecture with experience in: L1, L2 caches, Prefetch, Cache Coherent interconnect Fabric.
Large multi chip/system Cache Coherency experience, SOC/Multi-Chip Coherency Fabric and Memory Subsystem micro-architecture.
Deep understanding/experience of Coherent Interconnect Bus Architecture for CPU on-chip/off-chip network, MP coherency and last level system caches.
Strong RTL design expertise and hands-on experience of Processor/Asic design flow: design, verification, PD synthesis, ECO, bring up.