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Connect Pro Management Consultants
STA engineer
Connect Pro Management Consultants · posted 13 days ago
Bengalurusemiconductor
About the role
- Bachelor’s or Master’s degree in Electrical/Electronics Engineering, VLSI, Microelectronics, or a related field.
- Minimum 13+ years of relavent experience in STA full chip
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Core Tool Expertise (Mandatory):
- Sign-off STA: Synopsys PrimeTime (PT/PT-PX) and Cadence Tempus .
- Timing Closure / ECO: Cadence Tempus, Synopsys PrimeTime/PrimeClosure & Tweaker
- Constraints Validation: Synopsys TCM/GCA , Ausdia TimeVision , SpyGlass Constraints , or Cadence CCD
- Run strict constraints verification using industry-standard tools ( Synopsys TCM , SpyGlass Constraints , or Cadence CCD ) to eliminate unconstrained paths, incorrect clock-gating checks, and conflicting case analysis settings between functional and DFT model
- Hands-on experience reading, writing, and parsing Unified Power Format (UPF) constraints to validate low-power design architectures (e.g., power-gating, isolation cells, retention registers, and level-shifter placement
- Familiarity with Logic Equivalency Checking using industry tools like Cadence Conformal LEC or Synopsys Formality to verify that optimization/ECO steps maintain functional equivalence
- Deep understanding of advanced node variation models (POCV/LVF), temperature inversion, crosstalk/noise analysis, and hierarchical top-level clock distribution networks
- Solid comprehension of DFT architecture, test clock structures, multiplexer-heavy clock networks, and asynchronously driven test logic
- Expert proficiency in Tcl (highly critical for runtime timing script customization) and Python/Perl for automated data mining and constraint auditing