NXP-Bangalore/Noida/Pune_Verification_7 to 20years

NXP-Semiconductors-Bangalore/Noida/Pune. 

Website:  www.nxp.com 

Required details 

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2. Variable Pay/Annual Bonus - 

3. Unvested RSU & vesting period - 

4. Expected Base/Fixed pay - 

5. Notice Period (if serving-LWD) - 

6. Any offer in hand and offered Base/Fixed pay - 

7. Current location– 

8. Total years of experience- 

Job Description 

1. Principal DV Engineer 

Work Location: Bangalore/Noida/Pune

Experience: 13+years 

About the Team 

The Digital Engineering group is a highly collaborative organization comprising experienced ASIC and Systems engineers with deep expertise across architecture, logic design, verification, physical design, hardware–software co‑simulation, FPGA prototyping, and firmware development. The team brings together decades of cumulative industry experience and operates at the forefront of modern semiconductor design. 

We leverage advanced semiconductor process technologies and industry‑standard, state‑of‑the‑art EDA tools to deliver high‑quality silicon solutions. Our scope spans the full SoC development lifecycle, from architectural definition through verification, validation, and final product delivery. 

Senior/Staff ASIC Verification Engineer 

(Typically, 10–15 years of industry experience) 

Responsibilities 

·          Lead verification efforts for complex IPs or sub‑systems,  contributing to SoC‑level verification strategy under guidance from principal/architect‑level engineers. 

·          Design, develop, and maintain SystemVerilog/UVM‑based verification environments,  including agents, scoreboards, monitors, checkers, assertions, and functional coverage. 

·          Contribute to verification planning,  translating architectural specifications into detailed test plans and coverage models, and ensuring alignment with overall project verification goals. 

·          Develop UVM test sequences,  including constrained‑random, directed, and layered sequences, and participate in defining stimulus strategies to achieve coverage closure. 

·          Drive verification closure for owned blocks,  tracking functional, code, assertion, and power coverage, identifying gaps, and proposing corrective actions. 

·          Participate in low‑power verification flows,  including UPF/CPF integration and validation of power states and transitions at block and sub‑system levels. 

·          Support HW–FW co‑verification activities,  including development of C/C++ testcases for simulation, emulation, or FPGA prototyping, and assist with early firmware bring‑up. 

·          Debug complex RTL and gate‑level issues,  working closely with design and architecture teams to root‑cause functional, timing, and power‑related problems. 

·          Contribute to regression infrastructure,  including test triage, failure analysis, and improving regression efficiency and stability. 

·          Collaborate effectively with cross‑functional teams  (design, firmware, validation, and architecture) to ensure timely and high‑quality delivery. 

·          Mentor junior verification engineers,  providing technical guidance, code reviews, and best‑practice recommendations. 

Qualifications / Skills 

·          Strong track record of block or sub‑system verification ownership,  with experience contributing to multiple successful tape‑outs. 

·          Advanced proficiency in SystemVerilog and UVM,  with hands‑on experience building reusable and maintainable verification components. 

·          Solid understanding of ASIC verification methodologies, including: 

o     Verification planning and execution 

o     Directed and constrained‑random testing 

o     Functional, code, and assertion coverage 

o     Assertion‑based verification 

o     Low‑power verification using UPF/CPF 

·          Experience with C/C++‑based test development  for HW–FW simulation, emulation, or prototyping environments. 

·          Working knowledge of scripting languages  such as Python or Perl for automation, debug, and regression support. 

·          Familiarity with standard development and tracking tools,  including Git, Jira, and Confluence. 

·          Strong analytical and debugging skills,  with the ability to work independently on complex verification problems. 

·          Clear communication skills and a collaborative mindset,  capable of influencing technical decisions within the immediate team. 

Job Description 

2. Design Verification 

Work Location: Bangalore/Noida/Pune

Experience: 6 to 12+years 

Lead ASIC Verification Engineer 

The Digital Engineering group is a highly collaborative organization comprising experienced ASIC and Systems engineers with deep expertise across architecture, logic design, verification, physical design, hardware–software co‑simulation, FPGA prototyping, and firmware development. The team brings together decades of cumulative industry experience and operates at the forefront of modern semiconductor design. 

We leverage advanced semiconductor process technologies and industry‑standard, state‑of‑the‑art EDA tools to deliver high‑quality silicon solutions. Our scope spans the full SoC development lifecycle, from architectural definition through verification, validation, and final product delivery. 

Responsibilities 

·        Implement and execute verification for IP blocks and sub‑systems  using SystemVerilog and UVM, following established verification methodologies and plans. 

·        Develop and enhance UVM components,  including agents, monitors, drivers, scoreboards, assertions, and functional coverage models. 

·        Author and execute test plans and testcases,  including directed and constrained‑random tests, to validate functional correctness and corner cases. 

·        Contribute to verification closure,  analyzing coverage results, identifying gaps, and adding tests or coverage points to meet sign‑off requirements . 

·        Participate in low‑power verification,  assisting with UPF/CPF integration and validating power‑related scenarios under guidance. 

·        Assist in HW–FW co‑verification,  including development and execution of C/C++ tests for simulation or prototyping platforms. 

·        Debug RTL issues,  collaborating with design engineers to resolve functional mismatches, assertion failures, and coverage holes. 

·        Execute and maintain regressions, triaging failures and ensuring stability of the verification environment. 

·        Review specifications and design documents,  raising questions and identifying potential verification risks early in the development cycle. 

·         Work closely with peers and senior engineers,  contribute to team deliverables and continuously improving verification quality. 

Qualifications / Skills 

·          Hands‑on experience in ASIC/IP verification,  with at least one or more tape‑out cycles in a professional semiconductor environment. 

·          Good proficiency in SystemVerilog and UVM,  with experience developing test benches and testcases. 

·          Working knowledge of core verification concepts, including: 

o     Test planning and execution 

o     Directed and constrained‑random stimulus 

o     Functional and code coverage 

o     Basic assertion‑based verification 

o     Introduction to low‑power verification concepts 

·         Exposure to C/C++ programming  for verification or HW–FW interaction. 

·         Basic scripting skills  (Python, Perl, or similar) for automation and debug support. 

·         Experience using version control and issue‑tracking tools,  such as Git and Jira. 

·         Strong problem‑solving skills, attention to detail, and willingness to learn,  with the ability to take ownership of assigned verification tasks. 

·         Effective written and verbal communication skills , and ability to work well within a team environment.