About the role

Verification Engineer

Location:- Bangalore

Experience:- 6+Years

Job Responsibilities

Define comprehensive verification plans and build testbenches for device, subsystem, and IP-level designs using UVM/ SystemVerilog.
Interpret requirements, protocol specifications, and micro-architecture specifications to drive verification strategy.
Verify designs using state-of-the-art methodologies, including SystemVerilog/UVM coverage-driven verification, assertion-based verification (ABV), and formal verification techniques.
Execute simulations using Cadence Xcelium and perform debug using Cadence Verisium Manager.
Develop test cases, checkers, and functional coverage models aligned with the verification test plan.
Drive verification coverage closure and participate in coverage review meetings.
Collaborate with cross-functional teams including firmware, emulation, and silicon validation.
Support pre-silicon emulation bring-up and debug activities.
Support post-silicon validation bring-up and debug, including development and documentation of hardware workarounds.
Mentor junior engineers and contribute to team-level process improvements.

Requirements/Qualifications:

Required Qualifications

Bachelor's degree with 8–10 years of experience, or Master's degree with 6–8 years of experience in silicon verification.
Demonstrated expertise in RTL verification using coverage-driven verification ( CDV ) methodologies.
Proficiency in HDL/HVL languages: SystemVerilog, Verilog, or VHDL , industry protocols such as AXI, APB, AHB
Solid programming skills in C and/or C++.
Scripting experience in one or more languages (Python, Perl, TCL, Shell, etc.)
Strong understanding of digital systems and computer architecture.
Familiarity with Unix/Linux environments and version control systems (Git, SVN)
Excellent written and verbal communication and documentation skills.
Strong analytical and problem-solving skills with attention to detail.
Proven ability to work independently and collaboratively in a fast-paced team environment.

Preferred Qualifications

Hands-on experience with one or more industry protocols such as PCIe, CXL, NVMe, DDR, SAS, SATA.
Experience with formal verification tools (e.g., Cadence JasperGold, Synopsys VC Formal)
Prior experience in storage controller or memory controller verification
Experience mentoring or technically leading a small team