Power Architecture/Power Intent Expert

In your new role you will:
 

• Author and maintain power-intent files defining power domains, retention, isolation, level shifting, power switches, and sequencing for the Architecture of power efficient MCUs.
• Support UPF Methodology into RTL simulation, synthesis, static timing, place and route, formal, and DFT flows.
• Automate UPF generation, injection, linting, and regressions using Tcl/Python and CI/CD pipelines.
• Advise and train architects and RTL teams on power aware coding patterns and UPF best practices.
• Produce clear intent documentation, checklists, and sign off packages for handover IP-, SoC-, Verification- and Validation Teams.

You are best equipped for this task if you have:
 

• Minimum 7+  years of relevant work experience
• Strong expertise in  power architecture and RTL design
• In‑depth knowledge  of UPF (IEEE 1801) and power‑intent implementation
• Proficient in EDA flows , including  integration, validation, and troubleshooting of UPF across multiple power domains
• Advanced scripting and automation skills , with strong proficiency in Tcl and Python
• Hands‑on experience in cross‑domain debugging and sign‑off activities
• Solid AI/automation awareness , with demonstrated interest in leveraging emerging techniques to accelerate workflows, improve efficiency, and enhance data analysis