About the role

Job Description

Job Title: Lead Physical Design Engineer

Experience:- 6+Years

Primary Location: Hyderabad
Role Summary:
We are seeking a highly experienced Lead PD Engineer for AI NPU to lead and
contribute to the physical design and implementation of complex, high-performance
semiconductor integrated circuits. The individual is responsible from RTL synthesis,
Floor planning, Placement, CTS, Routing, Timing convergence (STA). The individual
contributes to problem solving related to physical design. Contributes to define best
Physical design strategy per technology node.
Job Responsibility:
* Execute physical design activities including floorplanning, power planning, place
and route, clock tree synthesis, and static timing analysis (STA).
* Collaborate with physical verification (DRC, LVS, Antenna) and resolve related
issues.
* Collaborate with power integrity analysis (IR drop, EM) and optimize designs for
power efficiency.
* Collaborate with design, verification, and DFT teams to ensure seamless
integration and achieve project milestones.
* Analyze and resolve design issues related to timing, area, and power.
* Develop and maintain scripts for automation and efficiency improvements in the
physical design flow.
* Contribute to the continuous improvement of physical design methodologies and
flows.
* Generate comprehensive reports and documentation of design implementation.

Job Qualification:

NXP Semiconductors, High Tech Campus 60, 5656 AG Eindhoven, The Netherlands INTERNAL
www.nxp.com
* Bachelor's or Master's degree in VLSI or Electronics Engineering or a related field.
* Minimum 8 years of experience in digital physical design of complex SoCs or ASICs.
* Proficiency with industry-standard EDA tools for physical design (e.g., Cadence
Innovus/Genus/Tempus or Synopsys Fusion Compiler/PrimeTime, Mentor Calibre).
* Solid understanding and experience of physical design concepts including
floorplanning, placement, routing, clock tree synthesis, and physical verification.
* Strong knowledge of Static Timing Analysis (STA) and timing closure techniques.
* Experience with scripting languages such as Tcl, Perl, or Python.
* Familiarity with deep sub-micron process technologies.
* Good understanding of VLSI design principles and semiconductor physics.
* Excellent problem-solving skills and attention to detail.
* Ability to work effectively in a collaborative team environment.
* Good communication skills, both written and verbal.