Sr. Engineer II – Verification

Job Description:

 

Microchip's Data Center Solutions Business Unit (DCS) maintains a broad portfolio of products widely deployed by the industry's leading server/storage OEMs and hyperscale data centers. Customers deploy DCS solutions into applications ranging from Big Data capacity storage to Artificial Intelligence and Machine Learning, technologies that are helping shape the next digital age. Our product portfolio includes SAS, PCIe, NVMe, and CXL products that connect, manage, and secure the world's information, including Flash Controllers, High-Performance Switches, RAID Controllers, and Memory Controllers.

 

As a Senior Verification Engineer, you will lead the development of verification environments for our next-generation Data Center Storage products, including enterprise-class NVMe SSD controllers and other PCIe-based products. These complex SoC silicon devices enable top-tier data centers across Next-Gen Storage, Artificial Intelligence, and High-Performance Computing market segments.

Job Responsibilities

• Define comprehensive verification plans and build testbenches for device, subsystem, and IP-level designs using UVM/ SystemVerilog.
• Interpret requirements, protocol specifications, and micro-architecture specifications to drive verification strategy.
• Verify designs using state-of-the-art methodologies, including SystemVerilog/UVM coverage-driven verification, assertion-based verification (ABV), and formal verification techniques.
• Execute simulations using Cadence Xcelium and perform debug using Cadence Verisium Manager.
• Develop test cases, checkers, and functional coverage models aligned with the verification test plan.
• Drive verification coverage closure and participate in coverage review meetings.
• Collaborate with cross-functional teams including firmware, emulation, and silicon validation.
• Support pre-silicon emulation bring-up and debug activities.
• Support post-silicon validation bring-up and debug, including development and documentation of hardware workarounds.
• Mentor junior engineers and contribute to team-level process improvements.

 

Requirements/Qualifications:

 

Required Qualifications

• Demonstrated expertise in RTL verification using coverage-driven verification (CDV) methodologies.
• Proficiency in HDL/HVL languages: SystemVerilog, Verilog, or VHDL , industry protocols such as AXI, APB, AHB
• Solid programming skills in C and/or C++.
• Scripting experience in one or more languages (Python, Perl, TCL, Shell, etc.)
• Strong understanding of digital systems and computer architecture.
• Familiarity with Unix/Linux environments and version control systems (Git, SVN)
• Excellent written and verbal communication and documentation skills.
• Strong analytical and problem-solving skills with attention to detail.
• Proven ability to work independently and collaboratively in a fast-paced team environment.

Preferred Qualifications

• Hands-on experience with one or more industry protocols such as PCIe, CXL, NVMe, DDR, SAS, SATA.
• Experience with formal verification tools (e.g., Cadence JasperGold, Synopsys VC Formal)
• Prior experience in storage controller or memory controller verification
• Experience mentoring or technically leading a small team