Principal Ethernet- Design Verification- 12+ yrs

Job Title- Principal Engineer, Design Verification Engineering 

Location - Bangalore

Exp- 12+yrs 

Skills- Ethernet architecture and protocols (MAC, PCS, PHY interfaces)

Job openings

Responsibilities 

o     Lead end-to-end SoC verification for complex digital SoCs, driving execution from planning to signoff. 

o     Verify complex microprocessor-based designs, AI/ML accelerators, and high-speed peripherals using advanced verification methodologies. 

o     Define and drive team execution by planning tasks, tracking progress, and providing technical leadership, mentoring, and guidance. 

o     Collaborate closely with architecture and design teams to define requirements and align on verification deliverables and dependencies. 

o     Drive pre-silicon readiness by aligning with emulation, FPGA, and software teams to cover post-silicon validation scenarios early. 

o     Develop and execute end-to-end system-level use cases for comprehensive functional validation. 

o     Architect and implement scalable UVM-based testbenches, DV flows, and methodologies. 

o     Define and review test plans; ensure closure of functional and code coverage across block, subsystem, and SoC levels. 

o     Work cross-functionally with emulation, FPGA, firmware, and system teams to ensure full-system correctness. 

o     Apply formal verification techniques for IP and subsystem-level validation. 

o     Lead NoC/interconnect verification and ensure robust data flow across the SoC. 

o     Perform performance verification and system-level analysis across real-world use cases. 

o     Drive innovation in verification strategies to meet aggressive schedules and quality goals. 

o     Define overall verification strategy based on product requirements and design specifications, leveraging modern techniques such as formal, emulation, portable stimulus, and virtual platforms. 

Requirements 

o     B.Tech/M.Tech with 12+ years of experience in digital pre-silicon verification, including leadership across IP, subsystem, or SoC-level DV. 

o     Strong understanding of SoC/Subsystem architectures with hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development, debugging, and methodology implementation. 

o     Proven track record in verification closure using functional and code coverage metrics across block, subsystem, and SoC levels. 

o     Expertise in NoC, bus, and interconnect verification, along with coverage analysis and optimization. 

o     Experience in architecting scalable testbench environments and defining robust DV flows and methodologies. 

o     Strong background in power-aware verification (UPF), including power analysis and optimization. 

o     Hands-on experience with formal verification, including flow definition, connectivity, and functional property checking. 

o     Solid protocol knowledge and verification experience across high-speed and low-speed interfaces such as I2C, SPI, Ethernet, UART, AXI/AHB, DMA, and SVI3. 

o     Experience in security and safety verification, ensuring compliance with secure design and functional safety requirements. 

o     Familiarity with gate-level simulations with timing annotation (GLS). 

o     Strong expertise in test planning, constrained-random verification, assertions, and transaction-level modeling. 

o     Good understanding of processor-based systems (ARM, RISC-V, Tensilica), AI/ML accelerators, and proficiency in C/C++, SystemC, and scripting (Python/TCL/Shell). 

o     Exposure to mixed-signal/analog verification (ADC/DAC/PLL/PHY) is a plus. 

o     Excellent communication and leadership skills with the ability to collaborate across global teams and drive verification innovation. 

o     Strong problem-solving mindset with the ability to quickly learn and adopt new technologies