IP Verification Engineer

Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.

 

 

Responsibilities:

 

• Lead the design and implementation of verification methodologies, test plans, testbenches, infrastructure, and platforms to produce thoroughly verified and robust products
• Partner closely with our architecture and design teams in specification and customer requirement reviews
• Represent verification methodologies in front of key customers and executive management
• Architect and help implement best verification practices, IP development and productization, quality assurance, release automation and improvements on the existing methodologies and flows
• Tackle sophisticated problems and develop scalable solutions that work across platforms
• Assist with all hardware project phases – bring-up, testing, debug, coverage analysis, and tracking
• Help with IP integration in partner environments and provide debug assistance to customer support teams

 

 

Qualifications:

 

• BS or MS degree in electrical or computer engineering or closely related degree strongly preferred; but substantial, relevant, outstanding work experience may substitute in some cases
• Eight to Ten years of experience working as a verification engineer or related field
• Strong written and verbal communication skills: ability to explain complex concepts in front of technical audience
• Strong desire to take ownership of all verification aspects of a project, including team and methodology leadership
• Exposure to block-level and/or system-level verification
• Highly technical competence that includes a track record of effective verification of complex digital designs
• Solid understanding of standard ASIC verification techniques, including:
  • Test planning
  • Testbench creation
  • Code and functional coverage
  • Directed and SystemVerilog-based constrained random stimulus generation
  • Self-checking – scoreboards, predictors, or reference models
  • Assertions
• Solid understanding of verification methodologies (UVM or OVM) and standard testbench languages
• Comfortable with Unix development environments (make, scripting, SVN, etc.), and with industry-standard EDA tools (VCS, Xcelium)
• Ability to support testbench lint/rule checking, profiling and automation using perl or python scripting
• Familiarity with advanced verification techniques such as object-oriented testbenches, fault/stimulus injection, FPGA prototyping and/or formal verification
• Protocol Knowledge
  • APB, AXI and AXI Stream
  • Ethernet/MACSec and IPSec
  • Crypto-Algorithm AES,SM4 ..etc

Experience leading multi-site teams and projects, including task and schedule estimation

Beneficial Experience:

• Experience in a customer-facing role
• Experience developing object-oriented testbench infrastructure in UVM
• Familiarity with IP integration, IP core delivery, and handoff issues
• Data, software, and/or network security; cryptography
• Ability to work with technical writers in the production of technical documentation