Infineon_Bangalore_Design Engineer_7+ Yrs

Your Role

Key responsibilities in your new role

 

• Responsible for STA and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets.
• Ownership of constraints development for functional/test modes at pre/post layout stage.
• Timing analysis and convergence of large hierarchical design across multiple modes and corners.
• Work closely with physical design team for timing/SI closure.
• Responsible for owning and/or mentoring Synthesis, Equivalence Checks.

 

Your Profile

Qualifications and skills to help you succeed

 

• Must have 8 + years of Strong exposure in constraints development, timing analysis/closure of large SoCs
• Expert user of industry standard tools for timing signoff
• Experience in scripting languages (shell, perl, tcl) and Make flow
• Understanding of 22nm/28nm/40nm technologies and associated timing/SI closure challenges
• Understanding of Low Power design techniques
• Experience in low-power synthesis and equivalence checks will be a plus