Radar IP design

Exp- 14YRS and above

 

 

Radar G5 IP design position:

 

Role Summary : Looking for a design engineer with strong DSP and radar signal-processing background to develop next-generation radar accelerators, FFT engines, and signal-processing IPs.

 

Technical Requirements (Radar IP RTL Designer)

• DSP Architecture & Hardware Acceleration
• FFT / IFFT Architecture Design
• Range FFT & Doppler FFT Processing
• CFAR  Detection
• Beamforming Algorithms
• Radar Signal Processing Chain
• MIMO Radar Processing
• Fixed-Point Arithmetic & Quantization
• Matrix/Vector Processing Architectures
• CORDIC Algorithms
• Data Compression & Decompression Techniques
• High-Performance Memory Architecture
• Hardware-Software Co-design for DSP Accelerators
• MATLAB/Python Based Algorithm Modeling
• RTL Design in Verilog/SystemVerilog
• ASIC/SoC Design Flow (Lint, CDC, STA, Synthesis)
• Performance, Power & Area (PPA) Optimization