RTL Design Engineer

 Senior Engineer II - Design 

Location:- Hyderabad

Experience:- 6+years

Job Description:

• Function : The design of ASIC blocks to be used within the next generation Microchip FPGA devices. These devices contain RiscV CPUs and all the associated functions to create true SOC functionality. It is expected that the successful candidate will be able to customize and integrate third-party IP blocks, and to create new ASIC blocks as required for the SOC and integration, involved from architecture through to production release. Integration also involves the design of compiled memories and integrating within the SOC along with memory MBIST.  The candidate must be familiar with Verilog/System Verilog coding and standard Synthesis and STA tools.
• The position will involve interaction with cross geography teams and cross functional teams like DFT and PnR and logic verification.

Skills :

• Experience in block level micro-architecture and RTL design of complex ASIC blocks.
• Experience in IP development from Scratch and integration into SOC.
• Experience in RTL development of industry standard protocols or IEEE standards.
• Experiencing in digital flows like linting, CDC, RDC, Synthesis, STA.
• Experienced in Verilog/ System Verilog coding, assertions and unit level verification.
• Good understanding of microprocessors and on-chip bus Structures (AXI, AMBA, peripheral interconnects and communication protocols)
• Experience is PCIe / USB is desired.
• RTL simulations and debugging experience.
• Deep understanding least three of
  • RiscV or ARM CPUs
  • Network On Chip Bus Interconnect (added plus point)
  • Ethernet
  • PCIe / USB
  • SD/MMC
  • DDR/LPDDR
  • High speed serial interfaces
  • IO, mixed signal designs
  • gearing logic

Requirements/Qualifications:

• 6+ years of professional experience in RTL design, linting, cdc, synthesis, STA
• Bachelor with Diploma in VLSI / Master of Engineering / Engineering Degree with experience in VLSI design