Sr. Principal SOC Architect

Sr. Principal SOC Architect 

Location- Bengaluru

Exp - 14+yrs 

Job Description 

Requirements

·          BE/MS in EE, CE, or related with 15–20 years in SoC architecture and/or technical leadership for hearables/ wearables/ audio ultra‑low‑power consumer / medical/ fitness devices.

·          Proven history of mixed‑signal SoCs development integrating AFEs, PMIC, and low‑power digital subsystems.

·          Experience in more than one of the following:

o     Analog/Mixed‑Signal: AFEs for mics/speakers/sensors, ADC/DAC architectures (SAR/ΣΔ), PLL/clocking, noise/jitter mitigation, layout‑aware design considerations.

o     Power: System power architecture, PMIC interaction, DVFS, multi‑domain power states, retention/isolation, leakage reduction, always‑on design.

o     Digital/Compute: DSP/CPU/MCU microarchitecture for audio/ML, memory hierarchy, bus/NoC design, QoS/latency guarantees, security primitives.

o     Audio & Sensors: ANC/beamforming fundamentals, audio quality metrics, PPG/IMU basics, and sensor fusion power/latency tradeoffs.

o     Standards/Stacks: Familiar with BLE/LE Audio, I²S/TDM/PDM, SoundWire; understanding codec chains (LC3, AAC, SBC) and voice pipelines.

·          Experience collaborating with customers and product development groups spread across the globe is a must; should have strong interpersonal and communication skills.

·          Systems thinking showcasing comfort balancing PPA with acoustics, human factors, RF coexistence, thermal, manufacturing, and cost.

·          Strong HW/SW co‑design mindset; experience guiding firmware policies for power state management and audio pipeline control.

·          Proficiency with MATLAB/Simulink, SystemC or transaction‑level modeling; power estimation; scripting (Python).

·          Data‑driven decision making with clear modeling assumptions and sensitivity analyses.

Responsibilities

·          Own end‑to‑end SoC architecture for hearables/wearables: sensor/analog front‑end → mixed‑signal → digital/compute → memory → power delivery → clocks → interfaces → security.

·          Translate product requirements (battery life, latency, SNR, ANC quality, thermal limits, size, cost) into SoC architecture, budgets, and roadmaps.

·          Write clear specs, conduct design reviews, and make data‑driven tradeoffs balancing PPA, schedule, and risk.

·          Define partitioning across die/tiles/3D IC/SiP/PoP with clear rationale for power, cost, yield, and schedule.

·          Select process nodes and options based on cost, leakage, variability, and long‑term supply.

·          Provide architectural leadership across analog, digital, RF, firmware, acoustics, product, test, and operations.

·          Set performance targets: SNR/THD+N, noise floor, linearity, dynamic range, CMRR/PSRR, jitter; validate via modeling and lab correlation plans.

·          Co‑optimize packaging, grounding, and isolation to minimize crosstalk, substrate noise, and coupled digital switching noise.

·          Architect compute for audio/voice/ML workloads: selection/partitioning of DSP/CPU/NN accelerators; fixed‑ vs floating‑point tradeoffs; memory hierarchy and scratchpad sizes.

·          Define low‑latency pipelines for ANC/beamforming/keyword spotting/echo cancellation with tight end‑to‑end latency and deterministic QoS.

·          Own security baseline (TRNG/PUF, secure boot, key storage, crypto accelerators) and always‑on domain for wake words/sensor fusion.

·          Mentor senior engineers; elevate design quality, docs, and reusable IP strategy.