ASIC RTL Design / Digital Design- 7+yrs

Location - Bangalore 

Job Role: ASIC Design / Digital Design 

Req Title : Principal / Senior Principal Engineer 

Exp- 7+yrs 

Job Description 

Key Responsibilities

Lead architecture definition and circuit design of OTP and EEPROM memory IPs, including bit-cell, periphery, high-voltage devices, charge pumps, sense amplifiers, and write/erase control.

Define programming algorithms, redundancy schemes, reliability mechanisms, and safety features.

Drive PPA (Power, Performance, Area) optimization across multiple technology nodes.

Own top-level NVM IP micro-architecture, including interfaces to digital controllers and test logic.

Responsibilities for Internal Candidates  

Implementation & Silicon Execution

Oversee schematic design, simulation, and verification (functional, corner, Monte-Carlo, aging).

Partner closely with layout teams to ensure DRC/LVS clean, robust HV-aware layouts with strong EM/IR and reliability margins.

Support DFT, BIST, IJTAG, and test-mode implementation, including fuse evaluation and trimming flows.

Drive silicon bring-up, debug, and characterization, including programming window optimization and yield learning.

Define and support qualification strategies (HTOL, bake, cycling, retention, endurance).

Work with Quality & Reliability teams to ensure product readiness and cost-effective qualification.

Own failure analysis and root-cause resolution for NVM-related issues.

Cross-Functional Leadership

Act as technical lead interfacing with Technology Development, Digital Design, Validation, Product, and Foundry partners.

Mentor junior and mid-level designers; establish best practices and design methodology for NVM IP.

Contribute to multi-generation NVM roadmaps and technology scaling strategies.

Qualifications for Internal Candidates     

Required Qualifications

Bachelor’s or Master’s degree in Electrical Engineering or related field.

10+ years of hands-on experience in OTP and/or EEPROM memory design.

Strong expertise in:

NVM bit-cell and peripheral circuit design

High-voltage devices and reliability-aware design

Programming/erase algorithms and margin analysis

Silicon debug and characterization

Proficiency with SPICE simulation, corner analysis, and statistical modeling.

Experience working across multiple process nodes and foundry technologies.

Preferred Qualifications