Principal Engineer-Synthesis, LEC, and Low power- PD- 10+yrs

 

Job Title - Principal Engineer

Exp - 10+yrs 

Location - Bangalore

 

Your role
Key responsibilities in your new role

 

• Develop, enhance, and maintain front-end design flows and automation frameworks to improve productivity and design quality
• Drive synthesis convergence and support design optimization across advanced technology nodes
• Perform design bring-up, debug, and issue resolution throughout the implementation cycle
• Execute and close Logic Equivalence Check (LEC) and low-power verification activities
• Collaborate closely with RTL, STA, DFT, and Physical Design (PD) teams to ensure seamless design integration and execution
• Analyze and debug design, flow, and tool-related issues, providing timely and scalable solutions
• Develop reusable methodologies, automation solutions, and best practices to improve design efficiency and scalability
• Support design signoff activities and ensure adherence to project timelines and quality goals

 

Your profile
Qualifications and skills to help you succeed 

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Microelectronics , or a related field
• 10+ years of experience in RTL-to-GDS (RTL2GDS) front-end implementation for complex SoC designs
• Strong technical expertise across the complete RTL2GDS design flow , with a deep understanding of front-end implementation methodologies
• Hands-on experience in Synthesis, LEC, and Low Power Verification (CLP) for large-scale and complex SoC projects
• Proven ability to proactively manage cross-functional dependencies, resolve technical conflicts, and effectively prioritize issues across multiple stakeholders
• Extensive experience with both Cadence (Genus, Conformal LEC/CLP) and Synopsys (Design Compiler/Fusion Compiler, Formality) tool flows
• Solid understanding of MCMM methodologies, UPF/CPF, timing constraints, power intent verification, and advanced-node implementation flows
• Strong programming and automation skills using Tcl, Python, and/or Perl , with demonstrated expertise in developing scalable and reusable automation solutions
• Excellent debugging and problem-solving skills, with the ability to drive synthesis convergence, closure activities, and design quality improvements
• Experience working closely with STA, DFT, Physical Design (PD), and RTL teams to ensure seamless project execution and successful tape-out