RTL FPGA Design-PCie

Responsibilities:

• Architect and develop Reference Designs and Solutions using Microchip FPGA products.
• Develop RTL and IP to implement the proposed designs.
• Define and implement use models for next-generation FPGA architecture exploration.
• Perform FPGA I/O interface (PCIe, Ethernet, DDR, XCVR, etc.) bring-up on FPGA hardware platforms.
• Execute the FPGA design flow, set timing constraints, and fix timing issues.
• Design debugging using tools and test equipment.
• Train Field Application Engineers on new product capabilities.
• Review and contribute to customer-facing product documentation and collateral.
• Adhere to defined development processes, quality standards, and coding guidelines.

 

Requirements/Qualifications:

 

• Bachelors or Masters in Electronics or Electrical Engineering with 10+ years of relevant experience

Required Skills:

• Strong proficiency in Verilog RTL design.
• Solid experience in digital logic design using FPGAs.
• Strong understanding of FPGA Design Flow, timing analysis and timing closure.
• Experience with one or more high-speed interfaces such as PCIe, Gigabit Ethernet, JESD204B/C, or DDR is desirable.
• Excellent debugging and problem-solving skills at both RTL and hardware levels.
• Hands-on experience using lab equipment such as protocol analyzers, clock generators, oscilloscopes, etc.
• Strong verbal and written communication skills.