Technical Staff – Verification Lead Engineer - 15yrs

 

Role - Technical Staff – Presilicon Verification Lead Engineer

Exp- 15+yrs

Location - Hyderabad

 

Job description

Key Responsibilities:

• Define and execute full chip verification for complex subsystems and SoC using an optimal combination of constrained random, formal and C based verification methodologies.  
• Architect and maintain highly reusable UVM based testbenches and verification environments.
• Drive RTL, Mixed mode, power aware and gate level verification activities.
• Develop and deploy AI/ML-enabled verification methodologies leveraging tools such as Siemens Fuse and Questa AI for predictive coverage, regression optimization, and debug automation.
• Collaborate with emulation and hardware prototyping teams to define a unified verification methodology .
• Collaborate with architecture and design teams to ensure seamless execution and first-silicon success.
• Mentor and lead a high-performing verification team , fostering innovation, technical excellence and career growth.

 

 

Requirements/Qualifications:

 

Required Qualifications:

• 15+ years in functional verification of complex SoC design; Leadership experience is mandatory.
• Expertise in System Verilog, UVM/OVM , formal verification methodologies
• Proven experience in methodology development and tool automation .
• Familiarity with AI/ML-driven EDA tools and scripting for flow integration.
• Highly Desirable: Strong understanding of FPGA architecture , high-speed interfaces (PCIe, Ethernet, DDR)

Desirable Skills

• Protocols & Domains:
  • PCIe Gen4/Gen5, DDR4/DDR5, LPDDR4X, MIPI DSI/CSI, Ethernet MAC, USB.
  • Security and cryptography IP integration.
  • ARM or RISC-V architecture.
• Advanced Capabilities:
  • Exposure to post-silicon debug , emulation , and hardware prototyping .
  • Experience with FPGA-based acceleration platforms and simulation/emulation flows.
• Software & Scripting:
  • Python, TCL/TK, and C/C++ for automation and validation.
• Tools:
  • Familiarity with Cadence/Mentor simulation suites and revision control systems (Git, Perforce).

Preferred Skills:

• Experience with coverage-driven verification using ML-based optimizations .
• Knowledge of predictive failure analysis and adaptive regression strategies .
• Ability to influence cross-functional teams and drive innovation in verification flows .

Preferred Attributes

• Strong analytical and problem-solving skills.
• Ability to lead cross-site teams and manage complex design programs.
• Excellent communication and collaboration skills for global team interaction.

 

Why Join Us?

• Work on cutting-edge FPGA and SoC technologies shaping next-generation computing.
• Opportunity to lead methodology innovation with AI/ML-driven verification flows.
• Collaborate with global teams and impact first-silicon success for flagship products.