DMS Verification

Digital Mixed Signal DV Engineer

About the job  

If you are looking to join an ingenious, vigorous & ambitious team that consistently delivers groundbreaking technologies into the custom mobile electronics world, here is an opportunity for you!   

Digital Design Verification (DV) Engineer

Location:  Bangalore, India

Experience:  2+Years

What will you be doing in this role?

Verification Strategy:  Drive the verification strategy, create detailed Test Plans, and develop comprehensive Test Benches for Chip Top levels.

UVM Architecture:  Responsible for grounds-up development of the DV environment, including coding UVM components like agents, drivers, monitors, and scoreboards.

Full-Cycle Execution:  Execute RTL and Gate Level Simulations (GLS), running regressions and tracking functional and code coverage (Block, Expression, Toggle, FSM) to achieve 100% closure. Worked on standard communication protocols like I2C, ASI, SPI, UART etc.

Technical Debugging:  Utilize excellent debugging and problem-solving skills to resolve complex design and testbench issues.

Post-Silicon Support:  Interact with Product and Application Engineering teams to support ATE functional pattern generation and silicon characterization.

Cross-Functional Collaboration:  Work closely with Architecture, Design, and Firmware teams to ensure successful product execution.

Qualifications

Basic Requirements (Must-Haves)

·          Education:  Bachelor’s or Master’s degree in Electrical Engineering (EE) or Electronics and Communication Engineering.

·          Experience:  Minimum 3 years of experience in IP-level and SoC-level Digital Design Verification.

·          Core Competencies:  Strong expertise in SystemVerilog (SV) and UVM methodologies.

·          Tools:  Proficiency with Cadence simulation tools and environments (e.g., Xcelium, Vmanager).

·          Communication:  Effective communication and interpersonal skills to interact with worldwide cross-functional experts and stakeholders.

Preferred Skills & "Good to Have" (Innovation & Automation)

·          Formal Verification (FV):  Experience with Formal property verification (FPV), Connectivity checks, and Unreachability (UNR) analysis for top-level sign-off.

·          Clock & Reset Domain:  Understanding of CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) assertions, with the ability to write and debug them.

·          Low Power Verification:  Specific experience with UPF (Unified Power Format) for low-power verification and power-aware simulations.

·          Automation Mindset:  Ability to automate verification flows and repetitive tasks using Python, Perl, or Shell scripting.

·          Mixed-Signal Exposure:  Basic knowledge or exposure to AMS (Analog Mixed-Signal) verification environments is an added advantage.

·          Methodology Innovation:  Ability to innovate and drive improved verification methodologies and work with EDA teams to upgrade tools. Exposure to building AI-driven verification methodologies.