Principal Digital Verification Engineer - 10+yrs

 

Job opening - Principal Digital Verification Engineer

EXP- 10+yrs

Location - Bangalore

 

 

Key Responsibilities

• Verification Ownership: Be responsible for the entire verification flow, from initial test plan creation to final product stream-out and silicon validation support .
• Methodology Development: Define and continuously improve the verification methodology and processes for digital designs.
• Framework Architecture: Define the architecture and lead the implementation of UVM-based verification frameworks .
• Code Implementation: Develop comprehensive code for UVM components, tests, sequences, Register Abstraction Layer (RAL), and functional coverage models. Code System Verilog Assertions (SVA) to enhance verification robustness.
• Execution & Analysis: Run verification regressions, thoroughly analyze results, and collaborate closely with design engineers to efficiently debug fail scenarios .
• Post-Silicon Support: Provide support for analytical debug of silicon during the prototype design phase.

Requirements/Qualifications:

Qualifications

Required Skills

• Technical Proficiency:
  • Expertise in UVM methodology.
  • Extensive experience in architecting and coding moderately complex UVM-based verification frameworks.
  • Proficiency in System Verilog coding .
  • Demonstrated ability to code System Verilog Assertions (SVA) .
• Soft Skills:
  • Must possess excellent problem-solving skills .
  • Must have good communication skills and the ability to work effectively and collaboratively in a team environment.
  • Must be self-motivated and committed to producing the best quality results.

 

Preferred Skills

• Scripting: Knowledge of and experience with scripting languages (e.g., Python, Perl, Tcl).
• Domain Knowledge: Experience working with memory products is highly preferable.
• Simulation Environment Expertise: Experience with mixed signal simulation environments is preferable.

 

Experience & Education

• Experience: Minimum of 10 years’ experience in UVM verification.
• Education: Bachelor’s degree or higher in Electrical Engineering