About the role

Principal Verification Engineer, Design

Location:- Hyderabad

Experience:- 10+Years

Our vision is to transform how the world uses information to enrich life for all .

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Responsibilities include, but not limited to:

Full-chip functional verification on Micron’s non-volatile memory design projects
You thoroughly understand design specs and develop verification plans for various designs.
Test bench Development in System Verilog targeting complete functionality coverage.
Support of System Verilog assertion and coverage-driven methodology
Support of design verification methodology improvements
Run directed and constrained-random verification tests.
You will think through design corner cases and be able to write relevant cover points.
Collaborate with digital design team to debug test cases and deliver functionally accurate designs.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Development of Micron’s NAND Flash behavioral models in System Verilog.
Technical support to internal and external model users
Complete verification on Micron’s NAND Flash models based on design datasheet.
Collaboration with Application engineers on design datasheet and model requirements
Driving innovation into the future Memory generations within a multifaceted work environment
Proven ability to leverage AI‑assisted (vibe) coding techniques to improve efficiency or automate design and analysis methodologies
Leverage AI tools to automate the tools and workflow

Applying Artificial Intelligence in workflows to improve build efficiency

Minimum Qualifications:

MS or BS degree in Electrical or Computer Engineering or equivalent
7-15 of experience developing verification collateral in Verilog, System Verilog and UVM
UVM Proficiency is a must.
Prior work experience with complex coverage driven random constraint UVM environments.
Putting together complex UVM environments from scratch is a requirement.
Deep knowledge on circuit design, digital logic, and logic verification methodology
Understanding on Verilog RTL coding, System Verilog object-oriented language
Good knowledge on programming language such as C++, and scripting language like TCL and PERL