Senior Lead/Staff/Sr. Staff/Principal Digital Design

Sr. Lead Digital Design

Location- Pune/Noida/Bengaluru

 

• The Digital Design Engineer is responsible for defining and realizing Digital functions on IPs, Subsystem or IC level based on required specifications.
• He is responsible for design, verification and evaluation of those. He is accountable for designing according to specifications, quality and reliability needs. Participation in problem solving for Digital and system domain of the device. Author of the design-specific documentation for internal and external use.
• The candidate will work as a design engineer for wireless/communication ASICs development.
• The main responsibilities include IP delivery and silicon validation support.
• The candidate may be working full ASIC design cycle from design, RTL coding, verification, synthesis, timing closure, DFT, backend support and silicon bring-up.

Principal Digital Design Engineer

Noida/Pune/Bengaluru

Responsibilities

 

• The Digital Design Engineer is responsible for defining and realizing Digital functions on IPs, Subsystem or IC level based on required specifications.
• He is responsible for design, verification and evaluation of those. He is accountable for designing according to specifications, quality and reliability needs. Participation in problem solving for Digital and system domain of the device. Author of the design-specific documentation for internal and external use.
• The candidate will work as a design engineer for wireless/communication ASICs development.
• The main responsibilities include IP delivery and silicon validation support.
• The candidate may be working full ASIC design cycle from design, RTL coding, verification, synthesis, timing closure, DFT, backend support and silicon bring-up.
  
   

Requirements

BSEE or equivalent required, MSEE is a plus, with 12+ years of related experience in following areas preferred:

 

• Strong Verilog/SystemVerilog coding skills
• Working knowledge of ASIC front-end design flows
• Working knowledge of C/C++
• Working experience of design verification techniques and test bench development
  
   

Strongly Desired

 

• Working knowledge of UVM is a desirable
• Good knowledge of System-Verilog assertions, checkers and other design verification techniques are a plus
• Working experience of Unified Power Format for simulation, synthesis and CLP checking is a plus
• Good knowledge of scripting languages. Perl and Python are plusses