Design Verification engineer

Qualifications:

• 2-5 years of DV experience in SS/SOC/Post silicon DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations

 

Skills:

·       Experience in one or many of the following: C based SOC DV, scripting (Python/Perl/Shell) knowledge, DV flow ownership for functional/Formal verification, UVM/System Verilog deep understanding, AMS/GLS/PAGLS/CPF/UPF based verification, Post silicon verification etc.

·       Strong in digital design fundamentals, computer organization & architectures and bus protocols

·       Excellent debugging skills with Verilog/VHDL designs

·       Thorough knowledge in one or many of the standard protocols. Ex: AXI, AHB, APB, CAN, Ethernet, I2C, SPI, UART, PSI5, Flexray etc

·       Work experience on C based environment with ARM/DSP multi-processor-based systems including the power aware simulations is a big plus

·       Good problem-solving skills 

·       Experience with Cadence tools (Xcelium/vManager/Formal applications/safety simulator) or similar tools/DV flows

·       Exposure to CDC DV, Post silicon verification and functional safety is an added advantage

·       Effective communication skills to interact seamlessly with all stakeholders

·       Must be highly focused and remain committed to obtaining closure on project goals