Staff Synthesis & STA Engineer

Staff Synthesis & STA Engineer

 

Location- Bengaluru

About the Role

As a Staff Synthesis & STA Engineer, you will own lead & own Synthesis & STA for complex high performance ICs with large digital & analog interfaces.

You'll influence implementation, guide methodology improvements, and lead small technical teams. This position requires deep expertise across multiple technical domains and strong cross-functional collaboration skills to drive innovation and excellence in digital design.

Key Responsibilities

• Digital Synthesis of high performance Digital blocks
• Timing constraint development, analysis, validation and debug 
• RTL to Netlist Logical equivalence check and debugging failures
• STA flow setup, convergence, reviews, flow optimization
• Timing, Noise, DRC (transition, capacitance) signoff for multi-mode, multi-corner
• Flow automation using TCL/Perl/Python
• Supporting Floor-planning, Placement, CTS, Routing, Extraction, Physical Verification, EM/IR flows, Signoff checks

Must Have Skills

• Hands on experience in Digital Synthesis, DFT insertion, Check Design and Check Timing Analysis
• Good understanding of all aspects of liberty models including power
• Ability to develop complex timing constraints by working with designers is a must. Should have experience in IP/subsystem/full-chip timing constraints
• Knowledge of commands and constructs supported across synthesis, STA , LEC and PD tools
• Analysis skills to root cause of timing violations issues and suggest solutions across various stages of design Implementation
• Hands on experience with the STA and Signoff of complex high speed SoC designs in cutting edge process technologies (16nm and below).
• Strong expertise in Timing ECOs driven by tool and manual ECO techniques for timing closure
• Sound understanding of Scan/DFT modes and timing
• Must have worked on Leakage and Dynamic power optimization of logic as part of Synthesis
• Must have worked on Synthesis/STA of 4+ successful tapeouts at lower geometries
• Familiar with digital flow design aspects RTL to GDS
• Proficiency in tcl/perl/python scripts and automation on timing analysis tools
• Flow enhancements to resolve timing and/or timing-DRC issues
• Hands on experience in Floor-planning, Placement, CTS, Routing using physical design tools, Extraction, Physical Verification, EM/IR flows, Signoff checks is desirable
• Good communication skills in cross-collaborative environment

Preferred Education and Experience

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering.
• 6-12 years of relevant experience.

Please share the following information along with your latest resume.

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