DDR PHY Sr Staff Design Verification - 10+yrs

 

Location - Bangalore

Exp- 10+yrs 

Experienced DDR-PHY Design Verification engineer to work on next generation System-on-chip (SoC) for smartphones, tablets, laptops.

Job responsibilities:

 

• 10+yrs of experience in Design Verification of complex IPs. Hands-on experience and very good understanding of DDRPHY architecture, DFI protocol and Jedec standards for latest Gens.
• Ownership of DV test bench and other associated collaterals (Checkers, Scoreboards, Assertion, Functional Coverage).
• Develop test plan and test cases to cover design feature set, follow up with stake holders at different levels of test bench.
• Work closely with Design, Subsystem/SOC, SVE teams on failure debugs, code/functional coverage closure, as well as DSF.
• Debug of regression signatures and identifying bug fixes.
• Responsible for Quality sign-off and required documentation.
• Debug and root cause SS/SOC/post silicon issues in collaboration with Design teams.
• Expertise in IP level /Sub-system level verification.
• Understanding of standard bus protocol like AHB, AXI protocols would be a plus.

 

 

Required skillset:

 

• Experience in verification and general computational logic design/verification concepts.
• Expertise in Verilog/System Verilog and UVM/OVM.
• Functional Verification, Coverage, Gate Simulation (GLS), Low Power Verification, Formal Verification 
• Strong debugging, Analytical and problem-solving skills.
• Experience in developing Monitors, Scoreboards, Sequencers that utilize System Verilog, and UVM methodologies for complex scenario generation and verification of DUT.
• Experience in Scripting languages like Perl /Tcl would be a plus.
• Post-si bring-up and HW-SW debug experience would be a plus.