Microchip-Bangalore_STA Synthesis_7 to 15years

JD

STA Synthesis

Experience: 7 to 15 years

Key Responsibilities:

·          Candidate will provide hands on technical contribution to the WSG Silicon Development Team in the area of design implementation.

·          Drive and optimize Synthesis, Formal, constraints, power optimization and STA for Microchip’s wireless SoC development.

·          Work closely with digital, analog, and physical design teams to optimize front-end (RTL-to-Netlist) implementation for performance, power, and area.

·          Drive front-end low power implementation and optimization using UPF.

·          Familiarity with multi-mode and corner timing closure, Signal integrity and noise analysis flows.

·          Previous experience with Microcontroller design is desirable.

·          Continuously improve RTL-to-Netlist tool flows and methodologies.

·          Interfacing with external vendors and IP sources to resolve problems.

·          Ability to work well in a team and excellent problem solving, verbal and written communication skills.

·          Working with members from international design and implementation teams

Requirements/Qualifications:

Requirements/Qualifications:

·          Bachelor’s in an engineering discipline plus 5+ years of experience or a Master’s in an engineering discipline plus 2.5 years of experience.

·          Expertise in Synthesis, Formal Verification and Static Timing Analysis, using industry leading tools.

·          Familiarity with Verilog, Verilog simulation, and debug.

·          Familiarity with Tcl, Perl, Python, and Shell scripting.

·          Solid understanding of digital implementation tools and flow

·          Good Communication and teamwork skills

·          Fluent in both written and spoken English

·          Knowledge and exposure to complete Silicon Tapeout flow is desired

·          We are looking for candidates who are self-motivators, energetic, and team players.

 

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