Design Verification -

Job Title - Design Verification 

location - Bangalore 

Exp- 2-5yrs 

Job Description 

What will you be doing in this role? (Responsibilities)
- Own part of IP DV from verification strategy to sign-off
- Coverage strategy & coverage closure (Functional, Code & Assertion coverage)
- Develop Test plans, verification strategy, test cases
- Use the right Verification strategy: Simulation, Formal, etc.
- Develop UVM components like agents, drivers, monitors and scoreboards
- Write assertion checks for DUT
- Use Formal apps like Connectivity, COV, UNR, FPV, etc.
- Debug the failures & report RTL bugs/Fix testbench
- Own the regressions for IP
- Improve the existing flows using latest methodologies/technologies

What do we expect from you? (Mini Qualifications)
- Bachelors/Masters in VLSI or related field
- 2- 5+. Of Digital Design Verification
- Strong command in System Verilog & UVM
- Creating DV environment or tests for IP-level digital DV/SoC level
- Developing DV testbenches, tests, assertion checking for DUT
- Experience in Verification tools like: Xcelium, JasperGold or similar
- Experience in Function & Code analysis & Closure
- Excellent debugging skills

- RTL Coding experience is a plus
- Experience in embedded memory verification is a plus
- Mixed digital/analog simulation (Verilog, AMS) is a plus
- Formal Verification experience is a plus
- Should be able to work with US Team
- Own part of IP DV from verification strategy to sign-off
- Coverage strategy & coverage closure (Functional, Code & Assertion coverage)
- Develop Test plans, verification strategy, test cases
- Use the right Verification strategy: Simulation, Formal, etc.
- Develop UVM components like agents, drivers, monitors and scoreboards
- Write assertion checks for DUT
- Use Formal apps like Connectivity, COV, UNR, FPV, etc.
- Debug the failures & report RTL bugs/Fix testbench
- Own the regressions for IP
- Improve the existing flows using latest methodologies/technologies