NXP-Pune_Physical Design_8 to 20years

Company Name:  NXP Semiconductors 

Website:  www.nxp.com 

Required details 

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2. Variable Pay/Annual Bonus - 

3. Unvested RSU & vesting period - 

4. Expected Base/Fixed pay - 

5. Notice Period (if serving-LWD) - 

6. Any offer in hand and offered Base/Fixed pay - 

7. Current location–

8. Total year of experience- 
 

1. Lead Physical Design Engineer 

Locations: Pune

Job Summary 
We are seeking a highly experienced Principal PD Engineer for iMCU & Connectivity to lead and contribute to the physical design and implementation of complex, high-performance semiconductor integrated circuits. This role involves driving technical solutions, mentoring junior engineers, and ensuring the timely delivery of cutting-edge products within NXP's diverse portfolio. 

Job Responsibilities 
As a Senior PD Engineer, your responsibilities will include but are not limited to: 
* Will be responsible for block level floor planning, power grid design, place and route, low power implementation, clock tree synthesis, timing closure, power/signal integrity analysis, to physical verification (DRC/LVS/Antenna). 

*The role would involve in-depth knowledge and responsibilities spanning all aspects of physical implementation.     

 * Drive the definition and implementation of physical design methodologies,  flows, and best practices to optimize performance, power, and area. 

* Perform comprehensive static timing analysis (STA) and ensure all timing constraints are met across various corners and modes. 

* Conduct power integrity (IR drop ) and signal integrity (Crosstalk) analysis and implement solutions to  mitigate issues. 

* Oversee and perform design rule checking (DRC), layout versus schematic (LVS), and other physical verification steps to ensure  tape-out readiness. 

* Collaborate closely with architecture, RTL design, DFT, and package teams to ensure seamless integration and successful product delivery. 

* Mentor and provide technical guidance to junior and senior physical design engineers, fostering a culture of continuous learning and excellence. 

* Evaluate and adopt new EDA tools and technologies to improve design efficiency and quality.  

 Job Qualifications             

 * Bachelor's degree with 9+ years of professional experience or Master's  degree with 8+ years of professional experience.  

* Working knowledge on advance tech nodes 16ff and below is highly desirable.  

 *Extensive knowledge and experience in back-end implementation tasks such as (timing & power), synthesis, low power implementation, power analysis, equivalence checking and STA.  

 *Experience at top-level will be added advantage. 

* Expert-level proficiency    with industry-standard EDA tools for physical design (e.g., Cadence Innovus,    Synopsys Fusion Compiler/ICC2, Ansys RedHawk/PowerSI). 

* Deep understanding    of Static Timing Analysis (STA) concepts, sign-off criteria, and tools (e.g., Synopsys PrimeTime).

 * Strong knowledge of power analysis and  optimization techniques (e.g., UPF/CPF, clock gating, power intent). 

*    Proven experience with physical verification tools (e.g., Synopsys IC Validator, Cadence Pegasus/PVS, Mentor Calibre). 

* Solid understanding of  semiconductor device physics, process technology effects, and DFM/DFY considerations. 

* Proficiency in scripting languages (e.g., Tcl, Python, Perl) for automation of design flows and analysis. 

* Excellent problem-solving, analytical, and debugging skills. 

* Strong communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and mentor other engineers. 

* Ability to work independently and take ownership of critical design aspects.  

2. Senior Principal Physical Design Engineer Company: NXP India Pvt. Ltd. (Pune) Job Summary As a Senior Principal Physical Design Engineer, you will be a key technical leader responsible for driving and executing advanced physical design activities for complex SoC and IP blocks. You will play a pivotal role in achieving challenging performance, power, and area targets for cutting-edge semiconductor products. Job Responsibilities * Lead and execute all aspects of physical design for large-scale digital designs from RTL to GDSII, including floor planning, power planning, place and route, clock tree synthesis, static timing analysis (STA), formal verification, design rule checking (DRC), and layout versus schematic (LVS). * Drive and optimize design methodologies, flows, and scripts to improve efficiency, turnaround time, and design quality. * Perform critical path analysis and provide innovative solutions to meet aggressive frequency and power targets. * Collaborate closely with design, architecture, and verification teams to ensure robust design implementation and resolve complex technical issues. * Mentor junior and mid-level engineers, providing technical guidance and fostering their growth within the physical design domain. * Evaluate and integrate new EDA tools and technologies to enhance physical design capabilities. * Contribute to defining and reviewing design specifications and architecture documents from a physical implementation perspective. * Develop and implement low-power design techniques (e.g., clock gating, power gating, multi-voltage design) to achieve challenging power budgets. * Generate comprehensive reports and documentation throughout the design cycle. Job Qualifications * Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field. * 15+ years of extensive experience in ASIC physical design with a strong track record of successful tape-outs on advanced process nodes. * Deep expertise in industry-standard EDA tools for physical design (e.g., Cadence Innovus/Tempus, Synopsys Fusion Compiler/PrimeTime, Ansys RedHawk/PathFinder). * Proficiency in scripting languages (Tcl, Perl, Python) for automation and flow development. * Strong understanding of static timing analysis concepts, constraints, and methodologies. * Hands-on experience with low-power design techniques and methodologies. * Solid understanding of semiconductor physics, process technology, and DFM (Design for Manufacturability) principles. * Demonstrated ability to lead technical initiatives and mentor other engineers. * Excellent problem-solving, analytical, and communication skills. * Ability to work effectively in a fast-paced, collaborative team environment.