ADI-Bangalore_Verification_7 to 17+years

Analog Devices-Bangalore. 

1. Staff Engineer, Design Verification Engineering 

About the Role 

Key member of design verification team  for SOC or subsystem design pre silicon verification.  The candidate will be responsible for formulating verification strategies, Define verification architecture, Flow, Methodology and leading, driving and completing verification of large integrated products. As a senior team member, it is expected that he/she will lead and influence verification methodologies within both DBU and ADI.   The candidate is also encouraged to participate in cross company technical initiatives as well as patent and publish work where possible. 

Responsibilities 

·          Lead pre-silicon verification for complex SoC or subsystem designs, driving execution from planning to closure. 

·          Verify microprocessor-based systems, AI/ML accelerators, and high-speed peripherals using advanced methodologies. 

·          Architect and implement UVM-based testbenches, DV flows, and scalable verification methodologies. 

·          Define and execute test plans; drive functional and code coverage closure in collaboration with design teams. 

·          Work cross-functionally with emulation, FPGA, and firmware teams to ensure end-to-end system correctness. 

·          Apply formal verification techniques for IP and subsystem-level validation. 

·          Lead NoC/interconnect verification and ensure robust data flow across the system. 

·          Perform system-level use case validation, including performance verification and analysis. 

·          Develop and validate end-to-end scenarios to ensure real-world functionality. 

·          Drive innovative verification strategies to meet quality and schedule goals. 

·          Define overall verification strategy based on product requirements and design specifications, leveraging modern techniques such as formal, emulation, portable stimulus, and virtual platforms. 

Requirements 

·          B.Tech/M.Tech with 8+ years of experience in digital pre-silicon verification. 

·          Strong understanding of SoC/subsystem architectures with hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development and debugging. 

·          Proven experience in verification closure using functional and code coverage metrics at block and subsystem levels. 

·          Expertise in NoC, bus, and interconnect verification, including coverage analysis and optimization. 

·          Experience in architecting testbench environments and implementing scalable DV flows and methodologies. 

·          Hands-on experience in power-aware verification using UPF, including power analysis and optimization. 

·          Exposure to formal verification, including flow setup, connectivity, and functional checks. 

·          Familiarity with gate-level simulations (GLS) with timing annotation. 

·          Strong knowledge of test planning, constrained-random verification, assertions, and transaction-level modeling using SystemVerilog. 

·          Understanding of processor-based systems (ARM, RISC-V, Tensilica), AI/ML or GPU-based architectures is a plus. 

·          Proficiency in C/C++, SystemC, and scripting (Python/TCL/Shell). 

·          Excellent communication and collaboration skills with the ability to work across global teams. 

·          Strong problem-solving ability with a mindset to quickly learn and adopt new technologies.

2. Principal Engineer, Design Verification 

Job Summary 

We are seeking a highly experienced Principal Verification Engineer to lead and drive functional verification for complex ASIC/SoC designs. This role requires deep technical expertise, strong architecture-level thinking, strong understanding of Ethernet specifications, and the ability to mentor teams while ensuring delivery of high-quality silicon. The ideal candidate will own verification strategy end-to-end and work closely with design, architecture, and post-silicon teams. The candidate will play a key role in ensuring standards compliance, performance, interoperability and robustness of ethernet products. 

Key Responsibilities 

Technical Leadership 

·          Define and own verification strategy and methodology (UVM/SystemVerilog) at IP, subsystem, and SoC levels 

·          Thoroughly understand and interpret Ethernet and related protocol specifications (IEEE standards, architecture specs, and micro-architecture documents) and translate them into comprehensive verification plans, assertions, and test scenarios 

·          Architect scalable verification environments , reusable VIPs, and checkers 

·          Drive coverage-driven verification , including functional, code, and assertion coverage 

·          Lead verification planning, testbench architecture, and test plan sign-off 

·          Identify, Review and guide complex test scenarios and corner cases 

Execution & Quality 

·          Ensure first-pass silicon success through rigorous functional and protocol compliance verification 

·          Drive bug triage, root-cause analysis, and closure across IP, Subsystem and SoC levels 

·          Define and track verification metrics, quality KPIs, and sign-off criteria 

·          Validate performance, stress, and corner scenarios such as congestion, backpressure, and error injection 

·          Support emulation, FPGA prototyping, and post-silicon validation for Ethernet bring-up and debug 

Cross-Functional Collaboration 

·          Work closely with architecture, RTL, DFT, physical design, firmware, and software teams 

·          Provide early verification input during architecture and micro-architecture definition , especially around standards compliance and performance assumptions 

·          Collaborate with software teams on driver, firmware, and traffic validation 

Mentorship & Process 

·          Mentor and technically guide verification engineers across experience levels 

·          Establish and enforce verification best practices and coding standards 

·          Drive continuous improvements in verification flows, reuse, and productivity 

Required Qualifications 

·          Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related field from reputed college 

·          10+ years of experience in ASIC/SoC design verification 

·          Strong hands-on expertise in SystemVerilog, UVM, and SVA 

·          Strong understanding of Ethernet architecture and protocols (MAC, PCS, PHY interfaces)

3. Principal Engineer, Design Verification Engineering 

About the Role 

Lead design verification team for SOC or subsystem design pre silicon verification.  The candidate will be responsible for formulating verification strategies, Define verification architecture, Flow, Methodology and leading, driving and completing verification of large integrated products. As a senior team member, it is expected that he/she will lead and influence verification methodologies within both DBU and ADI.   The candidate is also encouraged to participate in cross company technical initiatives as well as patent and publish work where possible. 

Responsibilities 

• Lead end-to-end SoC verification for complex digital SoCs, driving execution from planning to signoff. 
• Verify complex microprocessor-based designs, AI/ML accelerators, and high-speed peripherals using advanced verification methodologies. 
• Define and drive team execution by planning tasks, tracking progress, and providing technical leadership, mentoring, and guidance. 
• Collaborate closely with architecture and design teams to define requirements and align on verification deliverables and dependencies. 
• Drive pre-silicon readiness by aligning with emulation, FPGA, and software teams to cover post-silicon validation scenarios early. 
• Develop and execute end-to-end system-level use cases for comprehensive functional validation. 
• Architect and implement scalable UVM-based testbenches, DV flows, and methodologies. 
• Define and review test plans; ensure closure of functional and code coverage across block, subsystem, and SoC levels. 
• Work cross-functionally with emulation, FPGA, firmware, and system teams to ensure full-system correctness. 
• Apply formal verification techniques for IP and subsystem-level validation. 
• Lead NoC/interconnect verification and ensure robust data flow across the SoC. 
• Perform performance verification and system-level analysis across real-world use cases. 
• Drive innovation in verification strategies to meet aggressive schedules and quality goals. 
• Define overall verification strategy based on product requirements and design specifications, leveraging modern techniques such as formal, emulation, portable stimulus, and virtual platforms. 

Requirements 

• B.Tech/M.Tech with 12+ years of experience in digital pre-silicon verification, including leadership across IP, subsystem, or SoC-level DV. 
• Strong understanding of SoC/Subsystem architectures with hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development, debugging, and methodology implementation. 
• Proven track record in verification closure using functional and code coverage metrics across block, subsystem, and SoC levels. 
• Expertise in NoC, bus, and interconnect verification, along with coverage analysis and optimization. 
• Experience in architecting scalable testbench environments and defining robust DV flows and methodologies. 
• Strong background in power-aware verification (UPF), including power analysis and optimization. 
• Hands-on experience with formal verification, including flow definition, connectivity, and functional property checking. 
• Solid protocol knowledge and verification experience across high-speed and low-speed interfaces such as I2C, SPI, Ethernet, UART, AXI/AHB, DMA, and SVI3. 
• Experience in security and safety verification, ensuring compliance with secure design and functional safety requirements. 
• Familiarity with gate-level simulations with timing annotation (GLS). 
• Strong expertise in test planning, constrained-random verification, assertions, and transaction-level modeling. 
• Good understanding of processor-based systems (ARM, RISC-V, Tensilica), AI/ML accelerators, and proficiency in C/C++, SystemC, and scripting (Python/TCL/Shell). 
• Exposure to mixed-signal/analog verification (ADC/DAC/PLL/PHY) is a plus. 
• Excellent communication and leadership skills with the ability to collaborate across global teams and drive verification innovation. 
• Strong problem-solving mindset with the ability to quickly learn and adopt new technologies 

Screening Questions:

1.    How many years of hands-on pre-silicon verification experience do you have, and in what domains (SoC, IP, subsystem)?
              Red flag: Only IP-level or regression-only roles at this experience level.

2.    Have you built or architected UVM testbenches yourself (not just test writing)?

3.    How do you approach constrained-random verification and avoid over‑ or under‑constraining?
              Red flag: Only directed tests.

4.    What is your experience with UPF-based power-aware verification?
              Expected response on: Power states, isolation, retention, level shifters.

5.    How do you verify data integrity, ordering, and deadlock scenarios in NoC-based systems?
              Highly recommended: Assertions, monitors, stress scenarios.

6.    How many years of exp. In IP Verification and also specific IP on which you are proficient?

7.    Any exposure in Ethernet IP Verification and if yes what is total duration working on

CV Screening Format:

•           Candidate Name:

•           Total Experience:

•           Relevant Experience:

•           Current Company:

•           Current Role/Designation:

•           Key Skills Match (Yes/No – Details):

•           Domain Experience:

•           Strengths:

•           Gaps / Concerns:

•           Overall Screening Status (Shortlisted / Not Suitable):

•           Screener Comments:

Required details

1. Current annual Fixed pay -

2. Variable Pay/Annual Bonus -

3. Unvested RSU & vesting period -

4. Expected Base/Fixed pay -

5. Notice Period (if serving-LWD) -

6. Any offer in hand and offered Base/Fixed pay -

7. Current location -