About the role

Verification Manager

Location:- Bangalore

Expereince:- 12+years

Key Responsibilities

Strategic Leadership: Own the end-to-end verification strategy, from initial test plan development to final tape-out sign-off for multiple concurrent MCU projects.
Team Management: Lead and develop a global team of 20+ engineers. Manage resource allocation, performance reviews, and technical career growth.
Architecture Oversight: Define and refine scalable, reusable testbench architectures that support both simulation-based (UVM) and formal-based verification flows.
Technical Excellence: Drive the adoption of advanced techniques, including Formal Verification , Power-Aware Verification (UPF/CPF), and Hardware-Software Co-verification.
Cross-Functional Collaboration: Partner closely with Architecture, RTL Design, Digital Signal Processing (DSP), and Physical Design teams to resolve complex integration issues and architectural bottlenecks.
Methodology Innovation: Continuously improve verification efficiency through automation, Python/Perl scripting, and the integration of AI-driven verification tools.

Requirements/Qualifications:

Education: Bachelor of Science in Electrical Engineering or Computer Science, with strong digital design fundamentals.
Experience: 12+ years in SoC Verification, with at least 5 years in a formal leadership or management role.
Domain Expertise: Proven track record of successful tape-outs for 32-bit Microcontrollers . Deep understanding of MCU peripherals (DMA, Timers, ADC/DAC interfaces, Security modules).
Processor Knowledge: Direct experience verifying SoCs with ARM cores (Cortex-M) and proprietary RISC-based architectures.
Methodologies:
- Expert-level command of SystemVerilog and UVM (Universal Verification Methodology).
- Strong hands-on experience with Formal Verification (Property Checking, Connectivity Checking) using tools like JasperGold or VC Formal.
Protocol Proficiency: In-depth knowledge of AMBA bus protocols (AHB, APB, AXI).
Verification Infrastructure: Experience defining coverage-driven verification (CDV) metrics and managing massive regression suites. Module level verification plan development, TB plan, TB development and fullchip integration of the module level TB, develop effective functional assertions and coverpoints.

Preferred Skills

Strong background in Gate-Level Simulations (GLS) and power-aware verification.
Experience with Post-Silicon Validation, customer support and its alignment with pre-silicon test plans.
Experience with analog mixed-mode (AMS) simulations.
Familiarity with functional safety standards (ISO 26262) for automotive MCU applications.