Design Verification

Key Responsibilities

 

• Define and drive verification architecture and methodology for next generation HBM designs.
• Develop verification plans, coverage strategies, and sign-off criteria.
• Architect and implement UVM-based testbenches and reusable verification components.
• Apply Formal Verification techniques for critical
• Collaborate strictly with build teams to ensure verification completeness and quality.
• Mentor and guide verification engineers on guidelines and advanced methodologies.
• Evaluate and integrate AMS Co-Simulation techniques for mixed-signal IP verification.
• Work closely with EDA vendors to adopt the latest tools and flows.

 

Required Skills & Qualifications

 

• Expert-level proficiency in SystemVerilog, UVM, and advanced verification methodologies.
• Strong experience in Formal Verification tools and techniques.
• Solid understanding of SoC architecture, bus protocols (AXI, PCIe, etc.), and low-power build.
• Familiarity with AMS Co-Simulation and mixed-signal verification flows (preferred).
• Hands-on experience with simulation, coverage analysis, and regression management.
• Excellent problem-solving, debugging, and analytical skills.
• Proven ability to lead verification teams and influence technical direction.
• Comfortable using AI internal (Copilot/Claude)