Job Role: AMS Verification
Req Title : Principal AMS Verification
Experience : 5 to 15 yrs
BE in Electrical Engineering or related +6 years of experience, or MS + 5
years of experience in AMS verification
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Expert-level knowledge in Analog Mixed-Signal simulations
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Expert-level modeling of Analog blocks using SV Real Modeling /
Verilog-AMS /Verilog-A
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Proficient on using design and verification languages: Verilog,
System Verilog, and System Verilog Assertions (SVA).
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Proficient on Design Verification development process, from specification
to test plan, to configurable test bench, drivers and checkers
setup, to test suite building to meet functional and code coverage
goals
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Experience in verifying Power Management Blocks
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Proficiency in scripting languages such as PERL, TCL, Python
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Excellent communication skills with a collaborative and team-oriented
mindset
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Ability to quickly ramp on new systems and processes