ADI-Bangalore_STA Engineer_8 to 12+years

Analog Devices- Bangalore

Senior STA Engineer          

Senior Digital Design Engineer
About the Role
As a Senior Digital Design Engineer, you will lead block-level digital design synthesis and STA efforts. You'll be responsible for complex digital systems timing closure, and power optimization while mentoring junior engineers. This position requires deep understanding of digital design implementation methodologies, solve complex QoR challenges and achieve timing closure of block & full chip.

Key Responsibilities

o    Hands on experience in Digital Synthesis, DFT insertion, Check Design and Check Timing Analysis

o    Good understanding of all aspects of liberty models including power

o    Ability to develop complex timing constraints by working with designers is a must. Should have experience in IP/subsystem/full-chip timing constraints

o    Knowledge of commands and constructs supported across synthesis, STA , LEC and PD tools

o    Analysis skills to root cause of timing violations issues and suggest solutions across various stages of design Implementation

o    Hands on experience with the STA and Signoff of complex high speed SoC designs in cutting edge process technologies (16nm and below).

o    Strong expertise in Timing ECOs driven by tool and manual ECO techniques for timing closure

o    Good understanding of Scan/DFT modes and timing

o    Familiar with digital flow design aspects RTL to GDS

o    Proficiency in tcl/perl/python scripts and automation on timing analysis tools

o    Flow enhancements to resolve timing and/or timing-DRC issues

o    Hands on experience in Floor-planning, Placement, CTS, Routing using physical design tools, Extraction, Physical Verification, EM/IR flows, Signoff checks is desirable

o    Good communication skills in cross-collaborative environment

Must Have Skills

o    Timing Constraints Development : Hands on timing constraints development for complex blocks.

o    Timing Analysis and Closure: Strong capability in achieving timing closure on complex designs

o    Power Optimization: Practical experience optimizing digital designs for power efficiency

o    Strong troubleshooting skills

Preferred Education and Experience

o    Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent experience

o    4-6 years of relevant experience in Synthesis and STA.

Required details

1. Current annual Fixed pay-

2. Variable Pay/Annual Bonus-

3. Unvested RSU & vesting period-

4. Expected Base/Fixed pay-

5. Notice Period (if serving-LWD)-

6. Any offer in hand and offered Base/Fixed pay-

7. Current location-

8. Total years of experience-