Principal Engineer - Systems Validation

 

Excellent verbal and written communication skills in English-9 to 15yrs exp

·       Design with RTL coding in Verilog and VHDL and Verification of RTL

·       Possess an in-depth understanding of hardware architectures, system level IC design implementation, knowledge of how to create end use scenarios

·       Optimizing code for FPGA architectures

·       Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools

·       Basic knowledge of embedded processors such as ARM Cortex-M3 or RISC and familiarity with AMBA protocols APB, AHB, AXI, ACE

·       Working knowledge on embedded software C/C++ is also a plus

·       Strong technical background in FPGA prototype emulation, and debug

·       Strong technical background in silicon validation, failure analysis and debug

·       Excellent Board level debug capabilities in lab environment: hands-on troubleshooting skills for digital logic and analog circuit on PCB’s using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g. Synopsys Idenitfy, Xilinx Chipscope, Altera Signalscope, Lattice Reveal

·       Design with RTL coding in Verilog and VHDL is a must

·       Experience using Simulation (ModelSim/Questasim) and Synthesis (Synplicity) tools

 

Expertise in one of the areas mentioned below:

Memory Interfaces

Hands-on systems level design, debug and validation of following protocols:

• DDR4/LPDDR4/DDR5/LPDDR5 memories

Knowledge and working experience of DDR training algorithm

Experience with DDR memory controllers

knowledge of sideband I2C and I3C protocols