SOC Design leader & Principal engr- RTL Design

Experience : 10 – 15yrs

Roles : Chip Lead / SoC Design Leader

Location- G.Noida/Bengaluru

Job Description :

·          Drive architecture & application teams in converging to an optimal specification from performance, design effort/cost point of view. This includes detailed technical discussions and evaluations on IP choices and specifications, SoC architecture definitions covering different core and memory subsystems, solutions for clocking, power management, interconnect etc with target of PPA optimization to grant a competitive balance between product features and time-to-market. 

·          Close engagement with systems teams and customer interfaces to enable correct design decisions while working to build and develop system level knowledge within the design team. 

·          Conducts analyses covering feasibility studies, risk analysis, power, die size estimation etc.

·          Drive design implementation functions including sub-groups for RTL development and top integration, verification, performance evaluation and pre-Si validation, DFT, physical implementation team for execution of entire RTL2GDS flow. 

·          Running weekly reviews of open issues across development functions, closely monitoring and tracking, and provide technical leadership to individuals from outside the function and owning the outcome of the project

·          Manage project-related activities like design team meetings, project status reporting, project reviews  in compliance with product development lifecycle.

·          Collaborates with the teams across project core team members like engineering, validation, packaging, quality & reliability, marketing etc.

Technical skills/background:

·          Qualification: Bachelors/Masters in Electronics/Electrical Engineering

·          Experienced about system applications on aspects related to architectural choices in order to optimize for device performance, power and area. 

·          Good knowledge and understanding of advanced ARM real time and application CPU cores and memory subsystems, system bus architectures (like AHB/AXI), Arteris NOC and other interconnect technologies, debug subsystems, critical aspects like SoC clocking, reset and power mgmt., high speed SerDes, analog integration,  RTL design and SoC integration with multiple asynchronous clock domains,  bottlenecks identification, timing issues anticipation and resolution. 

·          Competent on power and clocking architectural concepts, capable of driving their definitions and anticipate potential implementation issues for high frequency designs. 

·          Design experience in mid-high complexity product developments in FDSOI 28nm, 16 FFC, 7nm technology nodes.

·          Knowledge of Automotive Functional Safety ISO26262 is a plus. 

Leadership Skills:

·          Proven track record of leadership role in managing high level complex designs, driving and coordinating across different teams.

·          Good negotiator and able to manage tough situations.

·          Adaptability to align and balance resources & time constraints according to business need.

·          Should possess strong communication skills to ensure effective interaction both with Management and internal project/design sub-groups members 

·          Good interpersonal skills.

·          Provide direction, mentoring, and leadership to small to medium-sized technical groups.

 

P           Principal Engineer- RTL design

Location- G.Noida/Bengaluru

Responsibilities and Qualifications for Internal Candidates

Job Description:

As part of the Platform design team, the Design Engineer will be responsible for leading and contributing to the design and delivery of Core Subsystem across multiple SoC generations. With deep experience in RTL design and SoC-level integration, this role is critical for enabling high-performance, low-power, and functionally safe systems across diverse markets.

Responsibilities

• Collaborate with systems architects and microarchitects to define high level, implementable SOC specifications.
• Own end-to-end IP/Sub-system RTL delivery while analyzing and optimizing design for power, performance and area (PPA) targets.
• Work on IPs including ARM Cores, Interconnect Fabrics, Memory Controller IPs.
• Lead RTL design and integration of Sub-system supporting complex architectures with multi-core, multi-reset domains.
• Demonstrate strong proficiency with frontend flows, including LINT, CDC, Synthesis, DFT and Static Timing Analysis (STA).
• Drive the development of robust Safety, Security and Debug architectures for advanced SOCs with multiple interconnects.
• Design and integrate standard interface protocols like AHB/AXI and memory interfaces like RAM, Flash.
• Engage cross-functionally with DFT, Physical Design, Verification, Emulation and Validation teams to ensure first time right silicon and on-time project delivery.
• Support silicon bring-up, debug, and post-silicon performance analysis through detailed simulation and system-level integration.
• Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle.
• Utilize scripting to manage design flows and automate repetitive tasks for improved efficiency. 
• Mentor junior engineers, and provide technical leadership and guidance across multiple design projects. 
• Contribute to the innovation quotient of the team via Patents, Industry standard publications etc.

Qualifications: 

• Bachelor's or Master’s degree or equivalent experience in Electronics/Electrical Engineering with 14-18 years of RTL design experience. 
• Hands on experience in RTL coding, debugging, verification, synthesis and timing closure. 
• Strong experience in ARM based SOC architecture and ASIC design flow
• AMBA protocols (AXI, AHB, APB), clock/reset domains and memory sub-systems.
• Experience with EDA tools for synthesis, LINT, CDC, RDC and timing analysis.
• Familiarity with formal verification techniques, static/dynamic power checks.
• Proficiency in scripting and automation using Python.
• Excellent leadership, communication skills.
• Experience working with global cross-functional teams.
• Working knowledge of safety-critical design flows in automotive systems. Knowledge of Automotive Functional Safety ISO26262 is a plus.