About the role

About TI

Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us – change the world, love your job!

About the Role:

We are seeking a skilled Digital Physical Design Engineer with around 4 years of industry experience in ASIC/SoC design. The candidate will be responsible for taking RTL through synthesis, floorplanning, place-and-route, timing closure, power optimization, and physical verification to tape-out. This role demands hands-on expertise in EDA tools, physical design flows, and deep knowledge of digital VLSI concepts.

Key Responsibilities:

Execute RTL-to-GDSII physical design flow for complex SoC/ASIC blocks.
Perform logic synthesis, floorplanning, placement, clock tree synthesis (CTS), and routing.
Develop/support/update design constraints.
Drive timing closure across multiple corners and modes using static timing analysis (STA).
Optimize for area, power, and performance (PPA) at block and chip level.
Conduct physical verification: DRC, LVS, Antenna checks, IR-drop, and EM analysis.
Develop/support/update constraints.
Collaborate with RTL design, verification, and architecture teams to resolve design and implementation issues.
Provide EDA flow automation support (scripting in TCL/Perl/Python).
Contribute to design reviews, documentation, and sign-off processes for successful tape-out.

Required Skills & Qualifications:

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or related field.
8+ years of hands-on experience in physical design for ASIC/SoC.
Strong knowledge of CMOS, VLSI design fundamentals, and digital circuit concepts.
Proficiency in EDA tools such Cadence (Innovus, Tempus, Voltus), or equivalent.
Expertise in timing analysis, floorplanning, placement, CTS, routing, and optimization techniques.
Experience in signoff checks: DRC, LVS, IR drop, EM, noise analysis.
Strong scripting skills (Tcl, Perl, or Python) for flow automation.
Excellent problem-solving, debugging, and analytical skills.

Soft Skills:

Strong communication and collaboration skills.
Ability to work in a fast-paced, deadline-driven environment.
Self-motivated and detail-oriented with a commitment to quality.