Staff Engr/Principal, Design Verification Engineering

Staff Engineer/Sr. Staff/Principal- Design Verification Engineering

Location-India, Bangalore, Aveda Meta

About the Role

Key member of design verification team  for SOC or subsystem design pre silicon verification.  The candidate will be responsible for formulating verification strategies, Define verification architecture, Flow, Methodology and leading, driving and completing verification of large integrated products. As a senior team member, it is expected that he/she will lead and influence verification methodologies within both DBU and ADI.   The candidate is also encouraged to participate in cross company technical initiatives as well as patent and publish work where possible.

 

Responsibilities

o     Lead pre-silicon verification for complex SoC or subsystem designs, driving execution from planning to closure.

o     Verify microprocessor-based systems, AI/ML accelerators, and high-speed peripherals using advanced methodologies.

o     Architect and implement UVM-based testbenches, DV flows, and scalable verification methodologies.

o     Define and execute test plans; drive functional and code coverage closure in collaboration with design teams.

o     Work cross-functionally with emulation, FPGA, and firmware teams to ensure end-to-end system correctness.

o     Apply formal verification techniques for IP and subsystem-level validation.

o     Lead NoC/interconnect verification and ensure robust data flow across the system.

o     Perform system-level use case validation, including performance verification and analysis.

o     Develop and validate end-to-end scenarios to ensure real-world functionality.

o     Drive innovative verification strategies to meet quality and schedule goals.

o     Define overall verification strategy based on product requirements and design specifications, leveraging modern techniques such as formal, emulation, portable stimulus, and virtual platforms.

 

Requirements

o     B.Tech/M.Tech with 8+ years of experience in digital pre-silicon verification.

o     Strong understanding of SoC/subsystem architectures with hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development and debugging.

o     Proven experience in verification closure using functional and code coverage metrics at block and subsystem levels.

o     Expertise in NoC, bus, and interconnect verification, including coverage analysis and optimization.

o     Experience in architecting testbench environments and implementing scalable DV flows and methodologies.

o     Hands-on experience in power-aware verification using UPF, including power analysis and optimization.

o     Exposure to formal verification, including flow setup, connectivity, and functional checks.

o     Familiarity with gate-level simulations (GLS) with timing annotation.

o     Strong knowledge of test planning, constrained-random verification, assertions, and transaction-level modeling using SystemVerilog.

o     Understanding of processor-based systems (ARM, RISC-V, Tensilica), AI/ML or GPU-based architectures is a plus.

o     Proficiency in C/C++, SystemC, and scripting (Python/TCL/Shell).

o     Excellent communication and collaboration skills with the ability to work across global teams.

o     Strong problem-solving ability with a mindset to quickly learn and adopt new technologies.