Sr. Engr/Principal engr/Tech. Staff

Sr. Engr/Principal Engr/Technical Staff- RTL Design

Work Location- Bengaluru

JD-1

Key Responsibilities
 

• Develop and maintain RTL code for digital blocks under guidance from senior engineers.
  Assist in micro-architecture development and design documentation.
  Perform RTL simulation and debugging to validate functional correctness.
  Run and address Lint and CDC checks for owned blocks.
  Support logic synthesis and basic static timing analysis activities.
  Work with physical design teams during implementation and debug cycles.
  Follow low-power design guidelines and assist in power-aware RTL development.
  Assist in DFT implementation and reviews as per project requirements.
  Debug design and EDA tool issues with support from experienced engineers.
  Develop and maintain basic automation scripts using Tcl, Perl, or Awk.
   

Requirements/Qualifications:
 

• 4–6 years of experience in ASIC/SoC digital design .
  Strong fundamentals in digital logic design and RTL coding (SystemVerilog preferred).
  Hands-on experience with RTL simulation, lint, and CDC .
  Basic understanding of logic synthesis and timing concepts .
  Working knowledge of ASIC design flows from RTL to sign-off.
  DFT awareness and basic hands-on experience .
  Familiarity with scripting languages such as Tcl, Perl, and/or Awk .
  Experience with Cadence design environments is an asset.

 

JD-2

8 + yrs- RTL design Microchip Bangalore
R114-26 Principal Engineer - Design
Job Description:
 

• Develop 32-bit Microcontroller products from concept through stream-out
  Perform System Verilog RTL design to integrate modules at SoC level to build 32-bit Microcontroller products
  Design modules for 32-bit microcontrollers products
  Define, develop, improve design process flows and methodologies for continuous improvement 
  Simulate at the module level and SoC level to guarantee design objective specification functionality and timing
  Generate and maintain Micro architecture specification (MAS) at module and SoC level and other design flow documentation 
  Run and debug gate level simulations at SoC level
  Implement ECOs
  Work with Synthesis, STA, DFT, APR and Layout engineers to resolve physical design issues for floor-planning and final sign off
  Interface with and support cross functional teams  such as applications, product and test engineering, marketing, development systems, technology development, CAD, layout and other design organizations
  Debug silicon products in support of Release to Production
   

Requirements/Qualifications:
 

• Must be able to write reusable System Verilog RTL codes, follow design and DFT guidelines
  Must have knowledge of design for low power and design for test and manufacturing
  Must have detailed understanding of gate level simulation flow and timing paths
  Able to write C and Assembly code based tests to verify SoC functionality
  Able to write good documentation for micro-architecture specification (MAS) and design flows/methodologies
  Able to write SoC level verification test plans
  Able to provide constraints for synthesis and static timing analysis
  Able to run formal verification/equivalence checking
  Able to write functional test patterns for production test program
  Have scripting and automation skills  - Linux shell scripting, Perl, Tcl, Makefile
  Strong analytical, and problem solving skills, as well as hands-on SoC debugging / bring up skills
  Self-motivated, able to work independently, excellent communication skills, excellent presentation skills for design reviews and ability to excel in a team environment
  BE / B.Tech with 8 yrs+ experience. Masters is a plus.